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Commit d2574c33 authored by Mario Kleiner's avatar Mario Kleiner Committed by Alex Deucher
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drm/amd/display: In VRR mode, do DRM core vblank handling at end of vblank. (v2) 



In VRR mode, proper vblank/pageflip timestamps can only be computed
after the display scanout position has left front-porch. Therefore
delay calls to drm_crtc_handle_vblank(), and thereby calls to
drm_update_vblank_count() and pageflip event delivery, to after the
end of front-porch when in VRR mode.

We add a new vupdate irq, which triggers at the end of the vupdate
interval, ie. at the end of vblank, and calls the core vblank handler
function. The new irq handler is not executed in standard non-VRR
mode, so vblank handling for fixed refresh rate mode is identical
to the past implementation.

v2: Implement feedback by Nicholas and Paul Menzel.

Signed-off-by: default avatarMario Kleiner <mario.kleiner.de@gmail.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fdd1fe57

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -827,6 +827,7 @@ struct amdgpu_device { 
	/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */

	struct work_struct		hotplug_work;

	struct amdgpu_irq_src		crtc_irq;

	struct amdgpu_irq_src		vupdate_irq;

	struct amdgpu_irq_src		pageflip_irq;

	struct amdgpu_irq_src		hpd_irq;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+125 −3
Original line number Diff line number Diff line
@@ -315,6 +315,32 @@ static void dm_pflip_high_irq(void *interrupt_params) 
	drm_crtc_vblank_put(&amdgpu_crtc->base);

}



static void dm_vupdate_high_irq(void *interrupt_params)

{

	struct common_irq_params *irq_params = interrupt_params;

	struct amdgpu_device *adev = irq_params->adev;

	struct amdgpu_crtc *acrtc;

	struct dm_crtc_state *acrtc_state;



	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);



	if (acrtc) {

		acrtc_state = to_dm_crtc_state(acrtc->base.state);



		DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,

				 amdgpu_dm_vrr_active(acrtc_state));



		/* Core vblank handling is done here after end of front-porch in

		 * vrr mode, as vblank timestamping will give valid results

		 * while now done after front-porch. This will also deliver

		 * page-flip completion events that have been queued to us

		 * if a pageflip happened inside front-porch.

		 */

		if (amdgpu_dm_vrr_active(acrtc_state))

			drm_crtc_handle_vblank(&acrtc->base);

	}

}



static void dm_crtc_high_irq(void *interrupt_params)

{

	struct common_irq_params *irq_params = interrupt_params;
@@ -325,10 +351,23 @@ static void dm_crtc_high_irq(void *interrupt_params) 
	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);



	if (acrtc) {

		acrtc_state = to_dm_crtc_state(acrtc->base.state);



		DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,

				 amdgpu_dm_vrr_active(acrtc_state));



		/* Core vblank handling at start of front-porch is only possible

		 * in non-vrr mode, as only there vblank timestamping will give

		 * valid results while done in front-porch. Otherwise defer it

		 * to dm_vupdate_high_irq after end of front-porch.

		 */

		if (!amdgpu_dm_vrr_active(acrtc_state))

			drm_crtc_handle_vblank(&acrtc->base);

		amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);



		acrtc_state = to_dm_crtc_state(acrtc->base.state);

		/* Following stuff must happen at start of vblank, for crc

		 * computation and below-the-range btr support in vrr mode.

		 */

		amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);



		if (acrtc_state->stream &&

		    acrtc_state->vrr_params.supported &&
@@ -1447,6 +1486,27 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) 
				dm_crtc_high_irq, c_irq_params);

	}



	/* Use VUPDATE interrupt */

	for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {

		r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);

		if (r) {

			DRM_ERROR("Failed to add vupdate irq id!\n");

			return r;

		}



		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;

		int_params.irq_source =

			dc_interrupt_to_irq_source(dc, i, 0);



		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];



		c_irq_params->adev = adev;

		c_irq_params->irq_src = int_params.irq_source;



		amdgpu_dm_irq_register_interrupt(adev, &int_params,

				dm_vupdate_high_irq, c_irq_params);

	}



	/* Use GRPH_PFLIP interrupt */

	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;

			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
@@ -1532,6 +1592,34 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 
				dm_crtc_high_irq, c_irq_params);

	}



	/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to

	 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx

	 * to trigger at end of each vblank, regardless of state of the lock,

	 * matching DCE behaviour.

	 */

	for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;

	     i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;

	     i++) {

		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);



		if (r) {

			DRM_ERROR("Failed to add vupdate irq id!\n");

			return r;

		}



		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;

		int_params.irq_source =

			dc_interrupt_to_irq_source(dc, i, 0);



		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];



		c_irq_params->adev = adev;

		c_irq_params->irq_src = int_params.irq_source;



		amdgpu_dm_irq_register_interrupt(adev, &int_params,

				dm_vupdate_high_irq, c_irq_params);

	}



	/* Use GRPH_PFLIP interrupt */

	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;

			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
@@ -3224,12 +3312,41 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) 
	return &state->base;

}



static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)

{

	enum dc_irq_source irq_source;

	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	int rc;



	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;



	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;



	DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",

			 acrtc->crtc_id, enable ? "en" : "dis", rc);

	return rc;

}



static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)

{

	enum dc_irq_source irq_source;

	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);

	int rc = 0;



	if (enable) {

		/* vblank irq on -> Only need vupdate irq in vrr mode */

		if (amdgpu_dm_vrr_active(acrtc_state))

			rc = dm_set_vupdate_irq(crtc, true);

	} else {

		/* vblank irq off -> vupdate irq off */

		rc = dm_set_vupdate_irq(crtc, false);

	}



	if (rc)

		return rc;



	irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;

	return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
@@ -4763,7 +4880,11 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 
		 * While VRR is active, we must not disable vblank irq, as a

		 * reenable after disable would compute bogus vblank/pflip

		 * timestamps if it likely happened inside display front-porch.

		 *

		 * We also need vupdate irq for the actual core vblank handling

		 * at end of vblank.

		 */

		dm_set_vupdate_irq(new_state->base.crtc, true);

		drm_crtc_vblank_get(new_state->base.crtc);

		DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",

				 __func__, new_state->base.crtc->base.id);
@@ -4771,6 +4892,7 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 
		/* Transition VRR active -> inactive:

		 * Allow vblank irq disable again for fixed refresh rate.

		 */

		dm_set_vupdate_irq(new_state->base.crtc, false);

		drm_crtc_vblank_put(new_state->base.crtc);

		DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",

				 __func__, new_state->base.crtc->base.id);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+9 −0
Original line number Diff line number Diff line
@@ -182,6 +182,15 @@ struct amdgpu_display_manager { 
	struct common_irq_params

	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];



	/**

	 * @vupdate_params:

	 *

	 * Vertical update IRQ parameters, passed to registered handlers when

	 * triggered.

	 */

	struct common_irq_params

	vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];



	spinlock_t irq_handler_list_table_lock;



	struct backlight_device *backlight_dev;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

+22 −0
Original line number Diff line number Diff line
@@ -674,11 +674,30 @@ static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev, 
		__func__);

}



static int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev,

					   struct amdgpu_irq_src *source,

					   unsigned int crtc_id,

					   enum amdgpu_interrupt_state state)

{

	return dm_irq_state(

		adev,

		source,

		crtc_id,

		state,

		IRQ_TYPE_VUPDATE,

		__func__);

}



static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {

	.set = amdgpu_dm_set_crtc_irq_state,

	.process = amdgpu_dm_irq_handler,

};



static const struct amdgpu_irq_src_funcs dm_vupdate_irq_funcs = {

	.set = amdgpu_dm_set_vupdate_irq_state,

	.process = amdgpu_dm_irq_handler,

};



static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {

	.set = amdgpu_dm_set_pflip_irq_state,

	.process = amdgpu_dm_irq_handler,
@@ -695,6 +714,9 @@ void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev) 
	adev->crtc_irq.num_types = adev->mode_info.num_crtc;

	adev->crtc_irq.funcs = &dm_crtc_irq_funcs;



	adev->vupdate_irq.num_types = adev->mode_info.num_crtc;

	adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs;



	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;

	adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

+6 −1
Original line number Diff line number Diff line
@@ -81,6 +81,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { 
	.ack = NULL

};



static const struct irq_source_info_funcs vupdate_irq_info_funcs = {

	.set = NULL,

	.ack = NULL

};



#define hpd_int_entry(reg_num)\

	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

		.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
@@ -137,7 +142,7 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { 
		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\

		.ack_value =\

		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\

		.funcs = &vblank_irq_info_funcs\

		.funcs = &vupdate_irq_info_funcs\

	}



#define vblank_int_entry(reg_num)\