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Commit d239b10d authored by Horia Geantă's avatar Horia Geantă Committed by Herbert Xu
Browse files

crypto: caam - add register map changes cf. Era 10 



Era 10 changes the register map.

The updates that affect the drivers:
-new version registers are added
-DBG_DBG[deco_state] field is moved to a new register -
DBG_EXEC[19:16] @ 8_0E3Ch.

Signed-off-by: default avatarHoria Geantă <horia.geanta@nxp.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 57f00289

drivers/crypto/caam/caamalg.c

+33 −14
Original line number Diff line number Diff line
@@ -3135,7 +3135,7 @@ static int __init caam_algapi_init(void) 
	struct device *ctrldev;

	struct caam_drv_private *priv;

	int i = 0, err = 0;

	u32 cha_vid, cha_inst, des_inst, aes_inst, md_inst;

	u32 aes_vid, aes_inst, des_inst, md_vid, md_inst;

	unsigned int md_limit = SHA512_DIGEST_SIZE;

	bool registered = false;
@@ -3168,14 +3168,34 @@ static int __init caam_algapi_init(void) 
	 * Register crypto algorithms the device supports.

	 * First, detect presence and attributes of DES, AES, and MD blocks.

	 */

	if (priv->era < 10) {

		u32 cha_vid, cha_inst;



		cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);

		aes_vid = cha_vid & CHA_ID_LS_AES_MASK;

		md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;



		cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);

	des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT;

	aes_inst = (cha_inst & CHA_ID_LS_AES_MASK) >> CHA_ID_LS_AES_SHIFT;

		des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >>

			   CHA_ID_LS_DES_SHIFT;

		aes_inst = cha_inst & CHA_ID_LS_AES_MASK;

		md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;

	} else {

		u32 aesa, mdha;



		aesa = rd_reg32(&priv->ctrl->vreg.aesa);

		mdha = rd_reg32(&priv->ctrl->vreg.mdha);



		aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;

		md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;



		des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;

		aes_inst = aesa & CHA_VER_NUM_MASK;

		md_inst = mdha & CHA_VER_NUM_MASK;

	}



	/* If MD is present, limit digest size based on LP256 */

	if (md_inst && ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256))

	if (md_inst && md_vid  == CHA_VER_VID_MD_LP256)

		md_limit = SHA256_DIGEST_SIZE;



	for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
@@ -3196,8 +3216,8 @@ static int __init caam_algapi_init(void) 
		 * Check support for AES modes not available

		 * on LP devices.

		 */

		if ((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP)

			if ((t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK) ==

		if (aes_vid == CHA_VER_VID_AES_LP &&

		    (t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK) ==

		    OP_ALG_AAI_XTS)

			continue;
@@ -3236,8 +3256,7 @@ static int __init caam_algapi_init(void) 
		 * Check support for AES algorithms not available

		 * on LP devices.

		 */

		if ((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP)

			if (alg_aai == OP_ALG_AAI_GCM)

		if (aes_vid  == CHA_VER_VID_AES_LP && alg_aai == OP_ALG_AAI_GCM)

			continue;



		/*

drivers/crypto/caam/caamalg_qi.c

+28 −9
Original line number Diff line number Diff line
@@ -2462,7 +2462,7 @@ static int __init caam_qi_algapi_init(void) 
	struct device *ctrldev;

	struct caam_drv_private *priv;

	int i = 0, err = 0;

	u32 cha_vid, cha_inst, des_inst, aes_inst, md_inst;

	u32 aes_vid, aes_inst, des_inst, md_vid, md_inst;

	unsigned int md_limit = SHA512_DIGEST_SIZE;

	bool registered = false;
@@ -2497,14 +2497,34 @@ static int __init caam_qi_algapi_init(void) 
	 * Register crypto algorithms the device supports.

	 * First, detect presence and attributes of DES, AES, and MD blocks.

	 */

	if (priv->era < 10) {

		u32 cha_vid, cha_inst;



		cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);

		aes_vid = cha_vid & CHA_ID_LS_AES_MASK;

		md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;



		cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);

	des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT;

	aes_inst = (cha_inst & CHA_ID_LS_AES_MASK) >> CHA_ID_LS_AES_SHIFT;

		des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >>

			   CHA_ID_LS_DES_SHIFT;

		aes_inst = cha_inst & CHA_ID_LS_AES_MASK;

		md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;

	} else {

		u32 aesa, mdha;



		aesa = rd_reg32(&priv->ctrl->vreg.aesa);

		mdha = rd_reg32(&priv->ctrl->vreg.mdha);



		aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;

		md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;



		des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;

		aes_inst = aesa & CHA_VER_NUM_MASK;

		md_inst = mdha & CHA_VER_NUM_MASK;

	}



	/* If MD is present, limit digest size based on LP256 */

	if (md_inst && ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256))

	if (md_inst && md_vid  == CHA_VER_VID_MD_LP256)

		md_limit = SHA256_DIGEST_SIZE;



	for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
@@ -2556,8 +2576,7 @@ static int __init caam_qi_algapi_init(void) 
		 * Check support for AES algorithms not available

		 * on LP devices.

		 */

		if (((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP) &&

		    (alg_aai == OP_ALG_AAI_GCM))

		if (aes_vid  == CHA_VER_VID_AES_LP && alg_aai == OP_ALG_AAI_GCM)

			continue;



		/*

drivers/crypto/caam/caamhash.c

+15 −5
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * caam - Freescale FSL CAAM support for ahash functions of crypto API

 *

 * Copyright 2011 Freescale Semiconductor, Inc.

 * Copyright 2018 NXP

 *

 * Based on caamalg.c crypto API driver.

 *
@@ -1801,7 +1802,7 @@ static int __init caam_algapi_hash_init(void) 
	int i = 0, err = 0;

	struct caam_drv_private *priv;

	unsigned int md_limit = SHA512_DIGEST_SIZE;

	u32 cha_inst, cha_vid;

	u32 md_inst, md_vid;



	dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");

	if (!dev_node) {
@@ -1831,18 +1832,27 @@ static int __init caam_algapi_hash_init(void) 
	 * Register crypto algorithms the device supports.  First, identify

	 * presence and attributes of MD block.

	 */

	cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);

	cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);

	if (priv->era < 10) {

		md_vid = (rd_reg32(&priv->ctrl->perfmon.cha_id_ls) &

			  CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;

		md_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &

			   CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;

	} else {

		u32 mdha = rd_reg32(&priv->ctrl->vreg.mdha);



		md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;

		md_inst = mdha & CHA_VER_NUM_MASK;

	}



	/*

	 * Skip registration of any hashing algorithms if MD block

	 * is not present.

	 */

	if (!((cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT))

	if (!md_inst)

		return -ENODEV;



	/* Limit digest size based on LP256 */

	if ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256)

	if (md_vid == CHA_VER_VID_MD_LP256)

		md_limit = SHA256_DIGEST_SIZE;



	INIT_LIST_HEAD(&hash_list);

drivers/crypto/caam/caampkc.c

+7 −3
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * caam - Freescale FSL CAAM support for Public Key Cryptography

 *

 * Copyright 2016 Freescale Semiconductor, Inc.

 * Copyright 2018 NXP

 *

 * There is no Shared Descriptor for PKC so that the Job Descriptor must carry

 * all the desired key parameters, input and output pointers.
@@ -1017,7 +1018,7 @@ static int __init caam_pkc_init(void) 
	struct platform_device *pdev;

	struct device *ctrldev;

	struct caam_drv_private *priv;

	u32 cha_inst, pk_inst;

	u32 pk_inst;

	int err;



	dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
@@ -1045,8 +1046,11 @@ static int __init caam_pkc_init(void) 
		return -ENODEV;



	/* Determine public key hardware accelerator presence. */

	cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);

	pk_inst = (cha_inst & CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT;

	if (priv->era < 10)

		pk_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &

			   CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT;

	else

		pk_inst = rd_reg32(&priv->ctrl->vreg.pkha) & CHA_VER_NUM_MASK;



	/* Do not register algorithms if PKHA is not present. */

	if (!pk_inst)

drivers/crypto/caam/caamrng.c

+9 −1
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * caam - Freescale FSL CAAM support for hw_random

 *

 * Copyright 2011 Freescale Semiconductor, Inc.

 * Copyright 2018 NXP

 *

 * Based on caamalg.c crypto API driver.

 *
@@ -309,6 +310,7 @@ static int __init caam_rng_init(void) 
	struct platform_device *pdev;

	struct device *ctrldev;

	struct caam_drv_private *priv;

	u32 rng_inst;

	int err;



	dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
@@ -336,7 +338,13 @@ static int __init caam_rng_init(void) 
		return -ENODEV;



	/* Check for an instantiated RNG before registration */

	if (!(rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & CHA_ID_LS_RNG_MASK))

	if (priv->era < 10)

		rng_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &

			    CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;

	else

		rng_inst = rd_reg32(&priv->ctrl->vreg.rng) & CHA_VER_NUM_MASK;



	if (!rng_inst)

		return -ENODEV;



	dev = caam_jr_alloc();