Merge "ARM: dts: msm: update DSI PHY timings for panels on Lahaina" (d2330362) · Commits · e / devices / android_kernel_fairphone_FP5

display/lahaina-sde-display.dtsi

+22 −21

Original line number	Diff line number	Diff line
		@@ -193,7 +193,7 @@
		connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>;
		};

		/* PHY TIMINGS REVISION YB */
		/* PHY TIMINGS REVISION YC with reduced margins*/
		&dsi_sw43404_amoled_cmd {
		qcom,ulps-enabled;
		qcom,esd-check-enabled;
		@@ -206,8 +206,8 @@

		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05
		05 03 02 04 00 0f 0a];
		qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 13 05
		05 06 02 04 00 12 0a];
		qcom,display-topology = <2 2 1>;
		qcom,default-topology-index = <0>;
		qcom,partial-update-enabled = "single_roi";
		@@ -228,8 +228,8 @@

		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 11 05 05 08 08 05
		05 03 02 04 00 0f 0a];
		qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1e 05
		05 06 02 04 00 12 0a];
		qcom,display-topology = <2 2 1>;
		qcom,default-topology-index = <0>;
		};
		@@ -294,8 +294,8 @@
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 10 05 04 08 07 05
		05 03 02 04 00 0f 09];
		qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
		05 06 02 04 00 12 09];
		qcom,display-topology = <2 2 2>;
		qcom,default-topology-index = <0>;
		};
		@@ -314,8 +314,8 @@
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 12 05 05 09 08 05
		05 03 02 04 00 10 0a];
		qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 14 06
		06 07 02 04 00 15 0b];
		qcom,display-topology = <2 2 2>;
		qcom,default-topology-index = <0>;
		};
		@@ -334,8 +334,8 @@
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08
		08 05 02 04 00 17 0c];
		qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08
		08 08 02 04 00 1a 0c];
		qcom,display-topology = <1 0 1>;
		qcom,default-topology-index = <0>;
		qcom,mdss-dsi-panel-clockrate = <900000000>;
		@@ -445,8 +445,8 @@
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 15 06
		06 04 02 04 00 14 0b];
		qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06
		06 06 02 04 00 13 0a];
		qcom,display-topology = <2 2 2>;
		qcom,default-topology-index = <0>;
		};
		@@ -466,12 +466,10 @@
		qcom,mdss-dsi-display-timings {
		timing@0 {
		/*
		* Using PHY Timings version W as a
		* temporary solution for PHY timing issue that causes
		* corruption.
		* DPHY regular margins
		*/
		qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 06
		06 04 02 04 00 15 16];
		06 07 02 04 00 17 16 ];
		qcom,display-topology = <2 0 2>,
		<1 0 2>;
		qcom,default-topology-index = <0>;
		@@ -495,8 +493,8 @@
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 19 07 07 0c 0a 07
		07 05 02 04 00 15 0c];
		qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07
		07 08 02 04 00 18 0c];
		qcom,display-topology = <2 0 2>,
		<1 0 2>;
		qcom,default-topology-index = <0>;
		@@ -517,8 +515,11 @@
		qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1b 08 07 0d 0b 08
		08 05 02 04 00 17 0c];
		/*
		* DPHY regular margins
		*/
		qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21 07
		07 07 02 04 00 18 16];
		qcom,display-topology = <1 0 1>;
		qcom,default-topology-index = <0>;
		};