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Commit d1f61b15 authored by Deepak Kumar's avatar Deepak Kumar
Browse files

ARM: dts: msm: Add apb_pclk to GMU clock list for Shima 

apb_pclk is required to access QDSS registers. GMU need to add vote
before access can be made.

Change-Id: I26852622c0c453f56fe6d238a478283a0879e410
parent 1cf41137

qcom/shima-gpu.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -576,10 +576,12 @@ 
			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,

			<&gpucc GPU_CC_AHB_CLK>,

			<&gpucc GPU_CC_HUB_CX_INT_CLK>,

			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;

			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,

			<&aopcc QDSS_CLK>;



		clock-names = "gmu_clk", "cxo_clk", "axi_clk",

			"memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote";

			"memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote",

			"apb_pclk";



		mboxes = <&qmp_aop 0>;

		mbox-names = "aop";