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Commit d1f2b171 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull IOMMU updates from Joerg Roedel:

 - Debugfs support for the Intel VT-d driver.

   When enabled, it now also exposes some of its internal data
   structures to user-space for debugging purposes.

 - ARM-SMMU driver now uses the generic deferred flushing and fast-path
   iova allocation code.

   This is expected to be a major performance improvement, as this
   allocation path scales a lot better.

 - Support for r8a7744 in the Renesas iommu driver

 - Couple of minor fixes and improvements all over the place

* tag 'iommu-updates-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (39 commits)
  iommu/arm-smmu-v3: Remove unnecessary wrapper function
  iommu/arm-smmu-v3: Add SPDX header
  iommu/amd: Add default branch in amd_iommu_capable()
  dt-bindings: iommu: ipmmu-vmsa: Add r8a7744 support
  iommu/amd: Move iommu_init_pci() to .init section
  iommu/arm-smmu: Support non-strict mode
  iommu/io-pgtable-arm-v7s: Add support for non-strict mode
  iommu/arm-smmu-v3: Add support for non-strict mode
  iommu/io-pgtable-arm: Add support for non-strict mode
  iommu: Add "iommu.strict" command line option
  iommu/dma: Add support for non-strict mode
  iommu/arm-smmu: Ensure that page-table updates are visible before TLBI
  iommu/arm-smmu-v3: Implement flush_iotlb_all hook
  iommu/arm-smmu-v3: Avoid back-to-back CMD_SYNC operations
  iommu/arm-smmu-v3: Fix unexpected CMD_SYNC timeout
  iommu/io-pgtable-arm: Fix race handling in split_blk_unmap()
  iommu/arm-smmu-v3: Fix a couple of minor comment typos
  iommu: Fix a typo
  iommu: Remove .domain_{get,set}_windows
  iommu: Tidy up window attributes
  ...
parents 18d0eae3 2f2fbfb7

Documentation/admin-guide/kernel-parameters.txt

+12 −0
Original line number Diff line number Diff line
@@ -1759,6 +1759,18 @@ 
		nobypass	[PPC/POWERNV]

			Disable IOMMU bypass, using IOMMU for PCI devices.



	iommu.strict=	[ARM64] Configure TLB invalidation behaviour

			Format: { "0" | "1" }

			0 - Lazy mode.

			  Request that DMA unmap operations use deferred

			  invalidation of hardware TLBs, for increased

			  throughput at the cost of reduced device isolation.

			  Will fall back to strict mode if not supported by

			  the relevant IOMMU driver.

			1 - Strict mode (default).

			  DMA unmap operations invalidate IOMMU hardware TLBs

			  synchronously.



	iommu.passthrough=

			[ARM64] Configure DMA to bypass the IOMMU by default.

			Format: { "0" | "1" }

Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ Required Properties: 


    - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.

    - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.

    - "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU.

    - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.

    - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.

    - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.

Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt

+39 −0
Original line number Diff line number Diff line
@@ -9,6 +9,25 @@ blocks that can be used to create functional hardware objects/devices 
such as network interfaces, crypto accelerator instances, L2 switches,

etc.



For an overview of the DPAA2 architecture and fsl-mc bus see:

Documentation/networking/dpaa2/overview.rst



As described in the above overview, all DPAA2 objects in a DPRC share the

same hardware "isolation context" and a 10-bit value called an ICID

(isolation context id) is expressed by the hardware to identify

the requester.



The generic 'iommus' property is insufficient to describe the relationship

between ICIDs and IOMMUs, so an iommu-map property is used to define

the set of possible ICIDs under a root DPRC and how they map to

an IOMMU.



For generic IOMMU bindings, see

Documentation/devicetree/bindings/iommu/iommu.txt.



For arm-smmu binding, see:

Documentation/devicetree/bindings/iommu/arm,smmu.txt.



Required properties:



    - compatible
@@ -88,14 +107,34 @@ Sub-nodes: 
              Value type: <phandle>

              Definition: Specifies the phandle to the PHY device node associated

                          with the this dpmac.

Optional properties:



- iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier

  data.



  The property is an arbitrary number of tuples of

  (icid-base,iommu,iommu-base,length).



  Any ICID i in the interval [icid-base, icid-base + length) is

  associated with the listed IOMMU, with the iommu-specifier

  (i - icid-base + iommu-base).



Example:



        smmu: iommu@5000000 {

               compatible = "arm,mmu-500";

               #iommu-cells = <1>;

               stream-match-mask = <0x7C00>;

               ...

        };



        fsl_mc: fsl-mc@80c000000 {

                compatible = "fsl,qoriq-mc";

                reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */

                      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */

                msi-parent = <&its>;

                /* define map for ICIDs 23-64 */

                iommu-map = <23 &smmu 23 41>;

                #address-cells = <3>;

                #size-cells = <1>;

arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi

+6 −1
Original line number Diff line number Diff line
@@ -148,6 +148,7 @@ 
		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;



		clockgen: clocking@1300000 {

			compatible = "fsl,ls2080a-clockgen";
@@ -321,6 +322,8 @@ 
			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */

			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */

			msi-parent = <&its>;

			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */

			dma-coherent;

			#address-cells = <3>;

			#size-cells = <1>;
@@ -424,6 +427,9 @@ 
			compatible = "arm,mmu-500";

			reg = <0 0x5000000 0 0x800000>;

			#global-interrupts = <12>;

			#iommu-cells = <1>;

			stream-match-mask = <0x7C00>;

			dma-coherent;

			interrupts = <0 13 4>, /* global secure fault */

				     <0 14 4>, /* combined secure interrupt */

				     <0 15 4>, /* global non-secure fault */
@@ -466,7 +472,6 @@ 
				     <0 204 4>, <0 205 4>,

				     <0 206 4>, <0 207 4>,

				     <0 208 4>, <0 209 4>;

			mmu-masters = <&fsl_mc 0x300 0>;

		};



		dspi: dspi@2100000 {

arch/arm64/mm/dma-mapping.c

+5 −5
Original line number Diff line number Diff line
@@ -712,7 +712,7 @@ static void __iommu_sync_single_for_cpu(struct device *dev, 
	if (is_device_dma_coherent(dev))

		return;



	phys = iommu_iova_to_phys(iommu_get_domain_for_dev(dev), dev_addr);

	phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dev_addr);

	__dma_unmap_area(phys_to_virt(phys), size, dir);

}
@@ -725,7 +725,7 @@ static void __iommu_sync_single_for_device(struct device *dev, 
	if (is_device_dma_coherent(dev))

		return;



	phys = iommu_iova_to_phys(iommu_get_domain_for_dev(dev), dev_addr);

	phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dev_addr);

	__dma_map_area(phys_to_virt(phys), size, dir);

}
@@ -738,9 +738,9 @@ static dma_addr_t __iommu_map_page(struct device *dev, struct page *page, 
	int prot = dma_info_to_prot(dir, coherent, attrs);

	dma_addr_t dev_addr = iommu_dma_map_page(dev, page, offset, size, prot);



	if (!iommu_dma_mapping_error(dev, dev_addr) &&

	    (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)

		__iommu_sync_single_for_device(dev, dev_addr, size, dir);

	if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&

	    !iommu_dma_mapping_error(dev, dev_addr))

		__dma_map_area(page_address(page) + offset, size, dir);



	return dev_addr;

}