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Commit d1e082ff authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/bxt: Fix GRC code register field definitions 



This has been corrected in BSpec quite some time ago, but we missed it
somehow. The wrong field definitions resulted in configuring PHY0 with
an incorrect GRC value.

v2:
- Remove the FIXME comment, we left in the code exactly about this
  issue. (Ville)

CC: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-3-git-send-email-imre.deak@intel.com
parent e7968531

drivers/gpu/drm/i915/i915_reg.h

+3 −7
Original line number Diff line number Diff line
@@ -1375,14 +1375,10 @@ enum skl_disp_power_wells { 


#define _PORT_REF_DW6_A			0x162198

#define _PORT_REF_DW6_BC		0x6C198

/*

 * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them

 * after testing.

 */

#define   GRC_CODE_SHIFT		23

#define   GRC_CODE_MASK			(0x1FF << GRC_CODE_SHIFT)

#define   GRC_CODE_SHIFT		24

#define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)

#define   GRC_CODE_FAST_SHIFT		16

#define   GRC_CODE_FAST_MASK		(0x7F << GRC_CODE_FAST_SHIFT)

#define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)

#define   GRC_CODE_SLOW_SHIFT		8

#define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)

#define   GRC_CODE_NOM_MASK		0xFF