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Commit d19830a0 authored by Abhijit Kulkarni's avatar Abhijit Kulkarni Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: fix dsc/vdc register range for lahaina 

DSC and VDC-M sub-block registers are not on contiguous
address range. This change allows specifying the individual
register ranges for each sub-block.

Change-Id: I16a1c4b6ac3570d4f43e2ff99132055949574173
parent 821cbd78

bindings/sde.txt

+4 −0
Original line number Diff line number Diff line
@@ -223,19 +223,23 @@ Optional properties: 
- qcom,sde-dsc-enc:		Array of offset addresses for the available dsc

				encoder blocks. These offsets are calculated from

				the corresponding DSC base.

- qcom,sde-dsc-enc-size		A u32 value indicates the enc block offset range.

- qcom,sde-dsc-ctl:		Array of offset addresses for the available dsc

				ctl blocks. These offsets are calculated from

				the corresponding DSC base.

- qcom,sde-dsc-ctl-size		A u32 value indicates the ctl block offset range.

- qcom,sde-dsc-native422-supp:	Array of flags indicating whether corresponding dsc

				block can support native 422 and native 420

				encoding.

- qcom,sde-vdc-off:		A u32 offset address for the available vdc blocks.

						This offset is calculated from register "mdp_phys"

						defined in reg property.

- qcom,sde-vdc-enc-size		A u32 value indicates the enc block offset range.

- qcom,sde-vdc-enc:		A u32 offset address for the vdc encoder block. This offset is

						calculated from qcom,sde-vdc-off.

- qcom,sde-vdc-ctl:		A u32 offset address for the vdc ctl block. This offset is

						calculated from qcom,sde-vdc-off.

- qcom,sde-vdc-ctl-size		A u32 value indicates the ctl block offset range.

- qcom,sde-qdss-off:		A u32 offset indicates the qdss block offset.

- qcom,sde-dither-off:		A u32 offset indicates the dither block offset on pingpong.

- qcom,sde-dither-version:	A u32 value indicates the dither block version.

display/lahaina-sde.dtsi

+6 −2
Original line number Diff line number Diff line
@@ -95,11 +95,13 @@ 
		qcom,sde-cdm-size = <0x224>;



		qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>;

		qcom,sde-dsc-size = <0x140>;

		qcom,sde-dsc-size = <0x10>;

		qcom,sde-dsc-pair-mask = <2 1 4 3>;

		qcom,sde-dsc-hw-rev = "dsc_1_2";

		qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>;

		qcom,sde-dsc-enc-size = <0x100>;

		qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>;

		qcom,sde-dsc-ctl-size = <0x10>;

		qcom,sde-dsc-native422-supp = <0 0 1 1>;



		qcom,sde-dither-off = <0xe0 0xe0 0xe0
@@ -108,10 +110,12 @@ 
		qcom,sde-dither-size = <0x20>;



		qcom,sde-vdc-off = <0x7C000>;

		qcom,sde-vdc-size = <0xf10>;

		qcom,sde-vdc-size = <0x10>;

		qcom,sde-vdc-hw-rev = "vdc_1_1";

		qcom,sde-vdc-enc = <0x200>;

		qcom,sde-vdc-enc-size = <0x1C8>;

		qcom,sde-vdc-ctl = <0xf00>;

		qcom,sde-vdc-ctl-size = <0x10>;



		qcom,sde-sspp-type = "vig", "vig", "vig", "vig",

					"dma", "dma", "dma", "dma";