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Commit d17c0faf authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx8: move MEC doorbell range setting 



It's global, not queue specific, so move it out of the
kiq register init function.

Tested-and-Reviewed-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a545e491

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+12 −14
Original line number Diff line number Diff line
@@ -4942,20 +4942,6 @@ static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring) 
	WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo);

	WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, mqd->cp_hqd_pq_wptr_poll_addr_hi);



	/* enable the doorbell if requested */

	if (ring->use_doorbell) {

		if ((adev->asic_type == CHIP_CARRIZO) ||

		    (adev->asic_type == CHIP_FIJI) ||

		    (adev->asic_type == CHIP_STONEY) ||

		    (adev->asic_type == CHIP_POLARIS10) ||

		    (adev->asic_type == CHIP_POLARIS11) ||

		    (adev->asic_type == CHIP_POLARIS12)) {

			WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,

						AMDGPU_DOORBELL_KIQ << 2);

			WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,

						AMDGPU_DOORBELL_MEC_RING7 << 2);

		}

	}

	WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->cp_hqd_pq_doorbell_control);



	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
@@ -5082,6 +5068,18 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) 
			goto done;

	}



	if ((adev->asic_type == CHIP_CARRIZO) ||

	    (adev->asic_type == CHIP_FIJI) ||

	    (adev->asic_type == CHIP_STONEY) ||

	    (adev->asic_type == CHIP_POLARIS10) ||

	    (adev->asic_type == CHIP_POLARIS11) ||

	    (adev->asic_type == CHIP_POLARIS12)) {

		WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,

		       AMDGPU_DOORBELL_KIQ << 2);

		WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,

		       AMDGPU_DOORBELL_MEC_RING7 << 2);

	}



	r = gfx_v8_0_kiq_kcq_enable(adev);

	if (r)

		goto done;