Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d16da119 authored Nov 24, 2018 by Lijun Ou Committed by Jason Gunthorpe Dec 05, 2018

RDMA/hns: Eanble SRQ capacity for hip08



This patch configures the flags for enabling the
SRQ(Share Receive Queue) capacity as well as update the
verb of querying device for setting srq specifications.

Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>

parent b2d8754f

drivers/infiniband/hw/hns/hns_roce_device.h

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -196,6 +196,7 @@ enum {
	HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),		HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
	HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3),		HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3),
	HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4),		HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4),
			HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
	HNS_ROCE_CAP_FLAG_MW = BIT(7),		HNS_ROCE_CAP_FLAG_MW = BIT(7),
	HNS_ROCE_CAP_FLAG_FRMR = BIT(8),		HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
	HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),		HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
	@@ -680,6 +681,9 @@ struct hns_roce_caps {
	int num_qps; /* 256k */		int num_qps; /* 256k */
	int reserved_qps;		int reserved_qps;
	u32 max_wqes; /* 16k */		u32 max_wqes; /* 16k */
			u32 max_srqs;
			u32 max_srq_wrs;
			u32 max_srq_sges;
	u32 max_sq_desc_sz; /* 64 */		u32 max_sq_desc_sz; /* 64 */
	u32 max_rq_desc_sz; /* 64 */		u32 max_rq_desc_sz; /* 64 */
	u32 max_srq_desc_sz;		u32 max_srq_desc_sz;

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+6 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1354,8 +1354,13 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
	caps->local_ca_ack_delay = 0;		caps->local_ca_ack_delay = 0;
	caps->max_mtu = IB_MTU_4096;		caps->max_mtu = IB_MTU_4096;

			caps->max_srqs = HNS_ROCE_V2_MAX_SRQ;
			caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
			caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;

	if (hr_dev->pci_dev->revision == 0x21)		if (hr_dev->pci_dev->revision == 0x21)
	caps->flags \|= HNS_ROCE_CAP_FLAG_ATOMIC;		caps->flags \|= HNS_ROCE_CAP_FLAG_ATOMIC \|
			HNS_ROCE_CAP_FLAG_SRQ;

	ret = hns_roce_v2_set_bt(hr_dev);		ret = hns_roce_v2_set_bt(hr_dev);
	if (ret)		if (ret)

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+3 −0

Original line number	Original line	Diff line number	Diff line
	@@ -46,6 +46,9 @@

	#define HNS_ROCE_V2_MAX_QP_NUM 0x2000		#define HNS_ROCE_V2_MAX_QP_NUM 0x2000
	#define HNS_ROCE_V2_MAX_WQE_NUM 0x8000		#define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
			#define HNS_ROCE_V2_MAX_SRQ 0x100000
			#define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
			#define HNS_ROCE_V2_MAX_SRQ_SGE 0x100
	#define HNS_ROCE_V2_MAX_CQ_NUM 0x8000		#define HNS_ROCE_V2_MAX_CQ_NUM 0x8000
	#define HNS_ROCE_V2_MAX_CQE_NUM 0x10000		#define HNS_ROCE_V2_MAX_CQE_NUM 0x10000
	#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100		#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100

drivers/infiniband/hw/hns/hns_roce_main.c

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -220,6 +220,11 @@ static int hns_roce_query_device(struct ib_device *ib_dev,
	IB_ATOMIC_HCA : IB_ATOMIC_NONE;		IB_ATOMIC_HCA : IB_ATOMIC_NONE;
	props->max_pkeys = 1;		props->max_pkeys = 1;
	props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;		props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
			if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
			props->max_srq = hr_dev->caps.max_srqs;
			props->max_srq_wr = hr_dev->caps.max_srq_wrs;
			props->max_srq_sge = hr_dev->caps.max_srq_sges;
			}

	return 0;		return 0;
	}		}