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Commit d16c7f6f authored by Vivek Aknurwar's avatar Vivek Aknurwar
Browse files

clk: qcom: gpucc: Add support for HLOS1_VOTE_GPU_SMMU_CLK 



Add clock GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK for clients to be able to
request for the clock.

Change-Id: I5325608b392ce3d0cf8390d7a893322e0f051a71
Signed-off-by: default avatarVivek Aknurwar <viveka@codeaurora.org>
parent a267c2a3

drivers/clk/qcom/gpucc-lahaina.c

+21 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/clk.h>
@@ -46,6 +46,9 @@ static const struct alpha_pll_config gpu_cc_pll0_config = { 
	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -85,6 +88,9 @@ static const struct alpha_pll_config gpu_cc_pll1_config = { 
	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -446,6 +452,19 @@ static struct clk_branch gpu_cc_gx_vsense_clk = { 
	},

};



static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {

	.halt_reg = 0x5000,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x5000,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_hub_aon_clk = {

	.halt_reg = 0x1178,

	.halt_check = BRANCH_HALT,
@@ -538,6 +557,7 @@ static struct clk_regmap *gpu_cc_lahaina_clocks[] = { 
	[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,

	[GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,

	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,

	[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,

	[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,

	[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,

	[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,