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Commit d1518a1d authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gmc: move vram type fetching into sw_init 



early_init gets called before atom asic init so on non-posted
cards, the vram type is not initialized.

Reviewed-by: default avatarHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 354edd8e

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

+8 −8
Original line number Diff line number Diff line
@@ -903,14 +903,6 @@ static int gmc_v7_0_early_init(void *handle) 
	gmc_v7_0_set_gart_funcs(adev);

	gmc_v7_0_set_irq_funcs(adev);



	if (adev->flags & AMD_IS_APU) {

		adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

	} else {

		u32 tmp = RREG32(mmMC_SEQ_MISC0);

		tmp &= MC_SEQ_MISC0__MT__MASK;

		adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);

	}



	return 0;

}
@@ -927,6 +919,14 @@ static int gmc_v7_0_sw_init(void *handle) 
	int dma_bits;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->flags & AMD_IS_APU) {

		adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

	} else {

		u32 tmp = RREG32(mmMC_SEQ_MISC0);

		tmp &= MC_SEQ_MISC0__MT__MASK;

		adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);

	}



	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);

	if (r)

		return r;

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

+8 −8
Original line number Diff line number Diff line
@@ -863,14 +863,6 @@ static int gmc_v8_0_early_init(void *handle) 
	gmc_v8_0_set_gart_funcs(adev);

	gmc_v8_0_set_irq_funcs(adev);



	if (adev->flags & AMD_IS_APU) {

		adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

	} else {

		u32 tmp = RREG32(mmMC_SEQ_MISC0);

		tmp &= MC_SEQ_MISC0__MT__MASK;

		adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);

	}



	return 0;

}
@@ -887,6 +879,14 @@ static int gmc_v8_0_sw_init(void *handle) 
	int dma_bits;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->flags & AMD_IS_APU) {

		adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

	} else {

		u32 tmp = RREG32(mmMC_SEQ_MISC0);

		tmp &= MC_SEQ_MISC0__MT__MASK;

		adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);

	}



	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);

	if (r)

		return r;