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Commit d132d6d5 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Rafael J. Wysocki
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ACPI / LPSS: enable hard LLP for DMA 



Right now the DMA support of hard LLP (*) is fused. Enable it via specific
message sent to SoC at run time.

(*) Hard LLP stands for the multi-block transfer feature of DMA controller
supported by hardware.

Tested-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 4881f0ba

drivers/acpi/acpi_lpss.c

+5 −3
Original line number Diff line number Diff line
@@ -724,13 +724,14 @@ static int acpi_lpss_resume_early(struct device *dev) 
#define LPSS_GPIODEF0_DMA1_D3		BIT(2)

#define LPSS_GPIODEF0_DMA2_D3		BIT(3)

#define LPSS_GPIODEF0_DMA_D3_MASK	GENMASK(3, 2)

#define LPSS_GPIODEF0_DMA_LLP		BIT(13)



static DEFINE_MUTEX(lpss_iosf_mutex);



static void lpss_iosf_enter_d3_state(void)

{

	u32 value1 = 0;

	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;

	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;

	u32 value2 = LPSS_PMCSR_D3hot;

	u32 mask2 = LPSS_PMCSR_Dx_MASK;

	/*
@@ -774,8 +775,9 @@ static void lpss_iosf_enter_d3_state(void) 


static void lpss_iosf_exit_d3_state(void)

{

	u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3;

	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;

	u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |

		     LPSS_GPIODEF0_DMA_LLP;

	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;

	u32 value2 = LPSS_PMCSR_D0;

	u32 mask2 = LPSS_PMCSR_Dx_MASK;