Merge fa770c0c on remote branch

					instead of standard dcs type 0x0A.

- qcom,vdc-version:		An 8 bit value indicates the VDC version supported by panel. Bits[0.3]

					provides information about minor version while Bits[4.7] provides

					major version information. It supports only VDC rev 1(Major).1(Minor)

					major version information. It supports only VDC rev 1(Major).2(Minor)

					right now.

- qcom,vdc-version-release:		An 8 bit value indicated VDC version release. This has to be set to 0.

- qcom,vdc-slice-height:	An u32 value which indicates slice height. This should be atleast 16 lines.

		qcom,display-topology = <1 1 1>,

			                <2 2 1>;

		qcom,default-topology-index = <0>;

		qcom,vdc-version = <0x11>;

		qcom,vdc-version = <0x12>;

		qcom,vdc-version-release = <0>;

		qcom,vdc-slice-height = <256>;

		qcom,vdc-slice-width = <720>;

- compatible:           Should be "qcom,dp-display".

- reg:                  Base address and length of DP hardware's memory mapped regions.

- reg-names:            A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.

			"dp_phy" - DP PHY memory region.

			"dp_ahb" - AHB memory region.

			"dp_aux" - AUX memory region.

			"dp_link" - LINK memory region.

			"dp_p0" - PCLK0 memory region.

			"dp_phy" - PHY memory region.

			"dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.

			"dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.

			"dp_mmss_cc" - Display Clock Control memory region.

			"qfprom_physical" - QFPROM Phys memory region.

			"dp_pll" - USB3 DP combo PLL memory region.

			"usb3_dp_com" - USB3 DP PHY combo memory region.

			"hdcp_physical" - DP HDCP memory region.

			"dp_p1" - DP PCLK1 memory region.

			"gdsc" - DISPCC GDSC memory region.

- cell-index:           Specifies the controller instance.

- #clock-cells:         Denotes the DP driver as a clock producer (has one or more clock outputs)

- clocks:               Clocks required for Display Port operation.

- clock-names:          Names of the clocks corresponding to handles. Following clocks are required:

			"core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk",

			"core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk",

			"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent".

- gdsc-supply:		phandle to gdsc regulator node.

			"core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk",

			"link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",

			"strm0_pixel_clk", "strm1_pixel_clk".

- vdda-1p2-supply:		phandle to vdda 1.2V regulator node.

- vdda-0p9-supply:		phandle to vdda 0.9V regulator node.

- interrupt-parent	phandle to the interrupt parent device node.

- interrupts:		The interrupt signal from the DSI block.

- qcom,aux-en-gpio:			Specifies the aux-channel enable gpio.

- qcom,aux-sel-gpio:		Specifies the aux-channel select gpio.

- qcom,usbplug-cc-gpio:		Specifies the usbplug orientation gpio.

- qcom,aux-cfg0-settings:		Specifies the DP AUX configuration 0 settings. The first

					entry in this array corresponds to the register offset

					within DP AUX, while the remaining entries indicate the

- qcom,fec-feature-enable:	FEC feature enable control node.

- qcom,max-dp-dsc-blks:		An integer specifying the max. DSC blocks available for Display port.

- qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block.

- qcom,dp-usbpd-detection:	Phandle for the PMI regulator node for USB PHY PD detection.

- qcom,altmode-dev:         Phandle for the AltMode GLink driver.

- usb-controller:         Phandle for the USB controller.

- qcom,pll-revision:    PLL hardware revision.

- qcom,dp-aux-switch:		Phandle for the driver used to program the AUX switch for Display Port orientation.

- qcom,dp-hpd-gpio:		HPD gpio for direct DP connector without USB PHY or AUX switch.

- qcom,dp-gpio-aux-switch:      Gpio DP AUX switch chipset support.

- qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types"

					can be "core", "ctrl", and "phy". Within the same type,

- qcom,<type>-supply-entries:		A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types"

					can be "core", "ctrl", "pll" and "phy". Within the same type,

					there can be more than one instance of this binding,

					in which case the entry would be appended with the

					supply entry index.

display interfaces, e.g. Display Port, and the audio subsystem.

Optional properties:

- vdd_mx-supply:		phandle to vdda MX regulator node

- qcom,aux-en-gpio:			Specifies the aux-channel enable gpio.

- qcom,aux-sel-gpio:		Specifies the aux-channel select gpio.

- qcom,usbplug-cc-gpio:		Specifies the usbplug orientation gpio.

- qcom,ext-disp:		phandle for msm-ext-display module

- compatible:			Must be "qcom,msm-ext-disp"

- qcom,dp-low-power-hw-hpd:	Low power hardware HPD feature enable control node

- compatible : "qcom,msm-ext-disp-audio-codec-rx";

Example:

ext_disp: qcom,msm-ext-disp {

	compatible = "qcom,msm-ext-disp";

	ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {

		compatible = "qcom,msm-ext-disp-audio-codec-rx";

	};

	cell-index = <0>;

	compatible = "qcom,dp-display";

		gdsc-supply = <&mdss_core_gdsc>;

		vdda-1p2-supply = <&pm8998_l26>;

		vdda-0p9-supply = <&pm8998_l1>;

	qcom,dp-aux-switch = <&fsa4480>;

	qcom,ext-disp = <&ext_disp>;

	qcom,altmode-dev = <&altmode 0>;

	usb-controller = <&usb0>;

		reg =	<0xae90000 0xa84>,

	reg =   <0xae90000 0x0dc>,

			<0xae90200 0x0c0>,

			<0xae90400 0x508>,

			<0xae91000 0x094>,

			<0x88eaa00 0x200>,

			<0x88ea200 0x200>,

			<0x88ea600 0x200>,

			<0xaf02000 0x1a0>,

			<0x780000 0x621c>,

			<0x88ea030 0x10>,

			<0x88e8000 0x621c>,

			<0x0aee1000 0x034>;

		reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",

			"dp_mmss_cc", "qfprom_physical", "dp_pll",

			"usb3_dp_com", "hdcp_physical";

			<0x88ea000 0x200>,

			<0x88e8000 0x20>,

			<0x0aee1000 0x034>,

			<0xae91400 0x094>,

			<0xaf03000 0x8>;

	reg-names = "dp_ahb", "dp_aux", "dp_link",

				"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",

				"dp_mmss_cc", "dp_pll", "usb3_dp_com",

				"hdcp_physical", "dp_p1", "gdsc";

	interrupt-parent = <&mdss_mdp>;

	interrupts = <12 0>;

	#clock-cells = <1>;

	clocks =  <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,

				<&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

				<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

				<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,

				<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,

				<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,

			 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;

				<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>,

				<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,

				<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,

				<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;

	clock-names = "core_aux_clk", "core_usb_ref_clk_src",

			"core_usb_ref_clk", "core_usb_cfg_ahb_clk",

			"core_usb_pipe_clk", "ctrl_link_clk",

			"ctrl_link_iface_clk", "ctrl_crypto_clk",

			"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent";

				"core_usb_pipe_clk", "link_clk", "link_iface_clk",

				"pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",

				"strm0_pixel_clk", "strm1_pixel_clk";

		qcom,dp-usbpd-detection = <&pm8150b_pdphy>;

		qcom,ext-disp = <&ext_disp>;

	qcom,pll-revision = "5nm-v1";

	qcom,phy-version = <0x420>;

	qcom,dp-aux-switch = <&fsa4480>;

	qcom,fec-feature-enable;

	qcom,max-dp-dsc-blks = <2>;

	qcom,max-dp-dsc-input-width-pixs = <2048>;

		pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";

		pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;

		pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;

		qcom,aux-en-gpio = <&tlmm 43 0>;

		qcom,aux-sel-gpio = <&tlmm 51 0>;

		qcom,usbplug-cc-gpio = <&tlmm 38 0>;

		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	vdda-1p2-supply = <&L6B>;

	vdda-0p9-supply = <&L1B>;

	vdd_mx-supply = <&VDD_MXA_LEVEL>;

	qcom,ctrl-supply-entries {

	#address-cells = <1>;

			qcom,supply-name = "vdda-1p2";

			qcom,supply-min-voltage = <1200000>;

			qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <21800>;

				qcom,supply-disable-load = <4>;

			qcom,supply-enable-load = <21700>;

			qcom,supply-disable-load = <0>;

		};

	};

		qcom,phy-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <36000>;

				qcom,supply-disable-load = <32>;

			qcom,supply-min-voltage = <912000>;

			qcom,supply-max-voltage = <912000>;

			qcom,supply-enable-load = <115000>;

			qcom,supply-disable-load = <0>;

		};

	};

	qcom,core-supply-entries {

		#address-cells = <1>;

		#size-cells = <0>;

		qcom,core-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "refgen";

			qcom,supply-min-voltage = <0>;

			qcom,supply-max-voltage = <0>;

			qcom,supply-enable-load = <0>;

			qcom,supply-disable-load = <0>;

		};

	};

	qcom,pll-supply-entries {

		#address-cells = <1>;

		#size-cells = <0>;

		qcom,pll-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vdd_mx";

			qcom,supply-min-voltage =

					<RPMH_REGULATOR_LEVEL_TURBO>;

			qcom,supply-max-voltage =

					<RPMH_REGULATOR_LEVEL_MAX>;

			qcom,supply-enable-load = <0>;

			qcom,supply-disable-load = <0>;

		};

	};

};

				each interface.

- qcom,sde-sspp-linewidth:	A u32 value indicates the max sspp line width.

- qcom,sde-vig-sspp-linewidth:  A u32 value indicates the max vig sspp line width.

- qcom,sde-scaling-linewidth:	A u32 value indicates the max vig source pipe line width

				for scaling purposes.

- qcom,sde-mixer-linewidth:	A u32 value indicates the max mixer line width.

- qcom,sde-wb-linewidth:	A u32 value indicates the max writeback line width.

- qcom,sde-sspp-scale-size:	A u32 value indicates the scaling block size on sspp.

				<read enable, write enable> for cdp use cases in

				order of <real_time>, and <non_real_time>.

- qcom,sde-qos-cpu-mask:	A u32 value indicating desired PM QoS CPU affine mask.

- qcom,sde-qos-cpu-mask-performance:	Each bit represents a CPU mask. For example

					0xf represents 4 cpu cores. These cores can be

					silver or gold or gold+.

- qcom,sde-qos-cpu-dma-latency:	A u32 value indicating desired PM QoS CPU DMA latency in usec.

- qcom,sde-inline-rot-xin:	An integer array of xin-ids related to inline

				rotation.

				ordering block

				0: lower priority pipe has to be on the left for a given pair of pipes.

				1: priority have to be explicitly configured for a given pair of pipes.

- qcom,sde-limits:		A node that lists the limits for different properties. This node

				can have multiple child nodes. Each child node represents a

				specific usecase limit. The usecase can be defined for properties like

				sspp linewidth, bw limit etc.

				e.g. qcom,sde-limits

				-- qcom,sde-limit-name: name of the usecase

				-- qcom,sde-limit-cases: different usecases to be considered

				-- qcom,sde-limit-ids: respective ids for the above usecases

				-- qcom,sde-limit-values: usecase and value for different combinations

Bus Scaling:

- interconnects                 An array of 4 cell properties with the format of

    qcom,sde-dsc-off = <0x00081000 0x00081400>;

    qcom,sde-vdc-off = <0x7C000>;

    qcom,sde-vdc-size = <0xf10>;

    qcom,sde-vdc-hw-rev = "vdc_1_1";

    qcom,sde-vdc-hw-rev = "vdc_1_2";

    qcom,sde-vdc-enc = <0x200>;

    qcom,sde-vdc-ctl = <0xf00>;

    qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;

			  <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,

			  <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,

			  <0x3b0 16>;

    qcom,sde-scaling-linewidth = <2560>;

    qcom,sde-mixer-linewidth = <2560>;

    qcom,sde-sspp-linewidth = <2560>;

    qcom,sde-mixer-blendstages = <0x7>;

    qcom,sde-cdp-setting = <1 1>, <1 0>;

    qcom,sde-qos-cpu-mask = <0x3>;

    qcom,sde-qos-cpu-mask-performance = <0xf>;

    qcom,sde-qos-cpu-dma-latency = <300>;

    qcom,sde-vbif-off = <0 0>;

        qcom,sde-dspp-vlut = <0x0 0x00010000>;

    };

    qcom,sde-limits {

	qcom,sde-linewidth-limits{

		qcom,sde-limit-cases = "vig", "dma", "scaling", "inline_rot";

		qcom,sde-limit-ids= <0x1 0x2 0x4 0x8>;

		/* the qcom,sde-limit-values property consist of two values:

		one for the usecase and the other for the value. The usecase can be

		any combination of the values mentioned in qcom,sde-limit-ids.

		For eg: <0x5 2560> means usecase is 0x5 and value is 2560.

		0x5 = (0x1 | 0x4) = vig + scaling. Thus the linewidth for usecase

		vig + scaling  = 2560 */

		qcom,sde-limit-values = <0x1 4096>,

					<0x5 2560>,

					<0xd 1088>,

					<0x2 4096>;

	};

       qcom,sde-bw-limits{

		qcom,sde-limit-cases = "per_pipe", "total_bw", "vfe_on", "cwb_on";

		qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;

		qcom,sde-limit-values = <0x1 2600000>,

					<0x9 2600000>,

					<0x5 2600000>,

					<0xd 2600000>,

					<0x2 5800000>,

					<0xa 5500000>,

					<0x6 4400000>,

					<0xe 3900000>;

	};

    };

    qcom,sde-mixer-blocks {

        qcom,sde-mixer-gc = <0x3c0 0x00010000>;

    };

				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

				qcom,mdss-dsi-h-sync-pulse = <0>;

				qcom,compression-mode = "vdc";

				qcom,vdc-version = <0x11>;

				qcom,vdc-version = <0x12>;

				qcom,vdc-version-release = <0>;

				qcom,vdc-slice-height = <256>;

				qcom,vdc-slice-width = <720>;

				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

				qcom,mdss-dsi-h-sync-pulse = <0>;

				qcom,compression-mode = "vdc";

				qcom,vdc-version = <0x11>;

				qcom,vdc-version = <0x12>;

				qcom,vdc-version-release = <0>;

				qcom,vdc-slice-height = <256>;

				qcom,vdc-slice-width = <720>;