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Commit d0f5cc5d authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/execlists: Terminate the context image with BB_END 



In the aub trace utility, the context images are terminated with a
MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise.
Do the same for our protocontext image for completeness, and in passing
apply the magic bit for gen10 to mark the end of the context image.

Reported-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180730164325.12770-1-chris@chris-wilson.co.uk
parent c358514b

drivers/gpu/drm/i915/intel_lrc.c

+4 −0
Original line number Diff line number Diff line
@@ -2653,6 +2653,10 @@ static void execlists_init_reg_state(u32 *regs, 


		i915_oa_init_reg_state(engine, ctx, regs);

	}



	regs[CTX_END] = MI_BATCH_BUFFER_END;

	if (INTEL_GEN(dev_priv) >= 10)

		regs[CTX_END] |= BIT(0);

}



static int

drivers/gpu/drm/i915/intel_lrc_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ 
#define CTX_PDP0_LDW			0x32

#define CTX_LRI_HEADER_2		0x41

#define CTX_R_PWR_CLK_STATE		0x42

#define CTX_GPGPU_CSR_BASE_ADDRESS	0x44

#define CTX_END				0x44



#define CTX_REG(reg_state, pos, reg, val) do { \

	u32 *reg_state__ = (reg_state); \