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Commit d0d6d836 authored by Zhou Yanjie's avatar Zhou Yanjie Committed by Linus Walleij
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dt-bindings: pinctrl: Add JZ4760 and JZ4760B bindings. 



Add the pinctrl bindings for the JZ4760 Soc and
the JZ4760B Soc from Ingenic.

Signed-off-by: default avatarZhou Yanjie <zhouyanjie@zoho.com>
Link: https://lore.kernel.org/r/1563076436-5338-2-git-send-email-zhouyanjie@zoho.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent a0b447c1

Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt

+5 −2
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ naming scheme "PxN" where x is a character identifying the GPIO port with 
which the pin is associated and N is an integer from 0 to 31 identifying the

pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and

PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to

PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a

total of 192 pins.

PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 contains 6

GPIO ports, PA to PF, for a total of 192 pins.





Required properties:
@@ -21,6 +21,8 @@ Required properties: 
 - compatible: One of:

    - "ingenic,jz4740-pinctrl"

    - "ingenic,jz4725b-pinctrl"

    - "ingenic,jz4760-pinctrl"

    - "ingenic,jz4760b-pinctrl"

    - "ingenic,jz4770-pinctrl"

    - "ingenic,jz4780-pinctrl"

 - reg: Address range of the pinctrl registers.
@@ -31,6 +33,7 @@ Required properties for sub-nodes (GPIO chips): 


 - compatible: Must contain one of:

    - "ingenic,jz4740-gpio"

    - "ingenic,jz4760-gpio"

    - "ingenic,jz4770-gpio"

    - "ingenic,jz4780-gpio"

 - reg: The GPIO bank number.