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Commit d0ba4c01 authored by Dong Aisheng's avatar Dong Aisheng Committed by Mark Brown
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ASoC: mxs-saif: set a base clock rate for EXTMASTER mode work 



Set an initial clock rate for the saif internal logic to work
properly. This is important when working in EXTMASTER mode that
uses the other saif's BITCLK&LRCLK but it still needs a basic
clock which should be fast enough for the internal logic.

Signed-off-by: default avatarDong Aisheng <dong.aisheng@linaro.org>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent c2e1d907

sound/soc/mxs/mxs-saif.c

+15 −1
Original line number Original line Diff line number Diff line
@@ -427,8 +427,22 @@ static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 




	/* prepare clk in hw_param, enable in trigger */

	/* prepare clk in hw_param, enable in trigger */

	clk_prepare(saif->clk);

	clk_prepare(saif->clk);

	if (saif != master_saif)

	if (saif != master_saif) {

		/*

		* Set an initial clock rate for the saif internal logic to work

		* properly. This is important when working in EXTMASTER mode

		* that uses the other saif's BITCLK&LRCLK but it still needs a

		* basic clock which should be fast enough for the internal

		* logic.

		*/

		clk_enable(saif->clk);

		ret = clk_set_rate(saif->clk, 24000000);

		clk_disable(saif->clk);

		if (ret)

			return ret;



		clk_prepare(master_saif->clk);

		clk_prepare(master_saif->clk);

	}





	scr = __raw_readl(saif->base + SAIF_CTRL);

	scr = __raw_readl(saif->base + SAIF_CTRL);