Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d06d88cb authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: gpucc: Update the PLL 2x frequency 



The GPUCC PLL needs to lock at 2x the RCG frequency, thus update the RCG
divider to '2' to lock the PLL at 2x.

Change-Id: Iadeb8b03cf10c170efa8b11bf9aadc35f67ce736
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 5702001d

drivers/clk/qcom/gpucc-holi.c

+7 −7
Original line number Diff line number Diff line
@@ -200,13 +200,13 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { 
};



static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {

	F(253000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),

	F(355000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),

	F(430000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),

	F(565000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),

	F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),

	F(800000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),

	F(875000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),

	F(253000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(355000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(430000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(565000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(800000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	F(875000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),

	{ }

};