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Commit d03790f5 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'Lantiq-Intel-vrx200-support' 



Hauke Mehrtens says:

====================
Add support for Lantiq / Intel vrx200 network

This adds basic support for the GSWIP (Gigabit Switch) found in the
VRX200 SoC.
There are different versions of this IP core used in different SoCs, but
this driver was currently only tested on the VRX200 SoC line, for other
SoCs this driver probably need some adoptions to work.

I also plan to add Layer 2 offloading to the DSA driver and later also
layer 3 offloading which is supported by the PPE HW block.

All these patches should go through the net-next tree.

This depends on the patch "MIPS: lantiq: dma: add dev pointer" which
should go into 4.19.

Changes since:
v2:
 * Send patch "MIPS: lantiq: dma: add dev pointer" separately
 * all: removed return in register write functions
 * switch: uses phylink
 * switch: uses hardware MDIO auto polling
 * switch: use usleep_range() in MDIO busy check
 * switch: configure MDIO bus to 2.5 MHz
 * switch: disable xMII link when it is not used
 * Ethernet: use NAPI for TX cleanups
 * Ethernet: enable clock in open callback
 * Ethernet: improve skb allocation
 * Ethernet: use net_dev->stats

v1:
 * Add "MIPS: lantiq: dma: add dev pointer"
 * checkpatch fixes a all patches
 * Added binding documentation
 * use readx_poll_timeout function and ETIMEOUT error code
 * integrate GPHY firmware loading into DSA driver
 * renamed to NET_DSA_LANTIQ_GSWIP
 * removed some needed casts
 * added of_device_id.data information about the detected switch
 * fixed John's email address
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents aaf92530 14fceff4

Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt

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Lantiq GSWIP Ethernet switches

==================================



Required properties for GSWIP core:



- compatible	: "lantiq,xrx200-gswip" for the embedded GSWIP in the

		  xRX200 SoC

- reg		: memory range of the GSWIP core registers

		: memory range of the GSWIP MDIO registers

		: memory range of the GSWIP MII registers



See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of

additional required and optional properties.





Required properties for MDIO bus:

- compatible	: "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP

		  core of the xRX200 SoC and the PHYs connected to it.



See Documentation/devicetree/bindings/net/mdio.txt for a list of additional

required and optional properties.





Required properties for GPHY firmware loading:

- compatible	: "lantiq,gphy-fw" and "lantiq,xrx200-gphy-fw",

		  "lantiq,xrx200a1x-gphy-fw", "lantiq,xrx200a2x-gphy-fw",

		  "lantiq,xrx300-gphy-fw", or "lantiq,xrx330-gphy-fw"

		  for the loading of the firmware into the embedded

		  GPHY core of the SoC.

- lantiq,rcu	: reference to the rcu syscon



The GPHY firmware loader has a list of GPHY entries, one for each

embedded GPHY



- reg		: Offset of the GPHY firmware register in the RCU

		  register range

- resets	: list of resets of the embedded GPHY

- reset-names	: list of names of the resets



Example:



Ethernet switch on the VRX200 SoC:



gswip: gswip@E108000 {

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "lantiq,xrx200-gswip";

	reg = <	0xE108000 0x3000 /* switch */

		0xE10B100 0x70 /* mdio */

		0xE10B1D8 0x30 /* mii */

		>;

	dsa,member = <0 0>;



	ports {

		#address-cells = <1>;

		#size-cells = <0>;



		port@0 {

			reg = <0>;

			label = "lan3";

			phy-mode = "rgmii";

			phy-handle = <&phy0>;

		};



		port@1 {

			reg = <1>;

			label = "lan4";

			phy-mode = "rgmii";

			phy-handle = <&phy1>;

		};



		port@2 {

			reg = <2>;

			label = "lan2";

			phy-mode = "internal";

			phy-handle = <&phy11>;

		};



		port@4 {

			reg = <4>;

			label = "lan1";

			phy-mode = "internal";

			phy-handle = <&phy13>;

		};



		port@5 {

			reg = <5>;

			label = "wan";

			phy-mode = "rgmii";

			phy-handle = <&phy5>;

		};



		port@6 {

			reg = <0x6>;

			label = "cpu";

			ethernet = <&eth0>;

		};

	};



	mdio@0 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "lantiq,xrx200-mdio";

		reg = <0>;



		phy0: ethernet-phy@0 {

			reg = <0x0>;

		};

		phy1: ethernet-phy@1 {

			reg = <0x1>;

		};

		phy5: ethernet-phy@5 {

			reg = <0x5>;

		};

		phy11: ethernet-phy@11 {

			reg = <0x11>;

		};

		phy13: ethernet-phy@13 {

			reg = <0x13>;

		};

	};



	gphy-fw {

		compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";

		lantiq,rcu = <&rcu0>;



		gphy@20 {

			reg = <0x20>;



			resets = <&reset0 31 30>;

			reset-names = "gphy";

		};



		gphy@68 {

			reg = <0x68>;



			resets = <&reset0 29 28>;

			reset-names = "gphy";

		};

	};

};

Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt

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Lantiq xRX200 GSWIP PMAC Ethernet driver

==================================



Required properties:



- compatible	: "lantiq,xrx200-net" for the PMAC of the embedded

		: GSWIP in the xXR200

- reg		: memory range of the PMAC core inside of the GSWIP core

- interrupts	: TX and RX DMA interrupts. Use interrupt-names "tx" for

		: the TX interrupt and "rx" for the RX interrupt.



Example:



eth0: eth@E10B308 {

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "lantiq,xrx200-net";

	reg = <0xE10B308 0x30>;

	interrupts = <73>, <72>;

	interrupt-names = "tx", "rx";

};

MAINTAINERS

+9 −0
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@@ -8167,6 +8167,15 @@ S: Maintained 
F:	net/l3mdev

F:	include/net/l3mdev.h



LANTIQ / INTEL Ethernet drivers

M:	Hauke Mehrtens <hauke@hauke-m.de>

L:	netdev@vger.kernel.org

S:	Maintained

F:	net/dsa/tag_gswip.c

F:	drivers/net/ethernet/lantiq_xrx200.c

F:	drivers/net/dsa/lantiq_pce.h

F:	drivers/net/dsa/intel_gswip.c



LANTIQ MIPS ARCHITECTURE

M:	John Crispin <john@phrozen.org>

L:	linux-mips@linux-mips.org

arch/mips/lantiq/xway/dma.c

+0 −1
Original line number Diff line number Diff line
@@ -106,7 +106,6 @@ ltq_dma_open(struct ltq_dma_channel *ch) 
	spin_lock_irqsave(&ltq_dma_lock, flag);

	ltq_dma_w32(ch->nr, LTQ_DMA_CS);

	ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);

	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);

	spin_unlock_irqrestore(&ltq_dma_lock, flag);

}

EXPORT_SYMBOL_GPL(ltq_dma_open);

arch/mips/lantiq/xway/sysctrl.c

+7 −7
Original line number Diff line number Diff line
@@ -505,7 +505,7 @@ void __init ltq_soc_init(void) 
		clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);

		clkdev_add_pmu("1a800000.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);

		clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);

		clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);

		clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);

		clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);

		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);

	} else if (of_machine_is_compatible("lantiq,ar10")) {
@@ -513,11 +513,11 @@ void __init ltq_soc_init(void) 
				  ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());

		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);

		clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);

		clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |

		clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |

			       PMU_PPE_DP | PMU_PPE_TC);

		clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);

		clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY);

		clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY);

		clkdev_add_pmu("1e108000.gswip", "gphy0", 0, 0, PMU_GPHY);

		clkdev_add_pmu("1e108000.gswip", "gphy1", 0, 0, PMU_GPHY);

		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);

		clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);

		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
@@ -536,12 +536,12 @@ void __init ltq_soc_init(void) 
		clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);



		clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);

		clkdev_add_pmu("1e108000.eth", NULL, 0, 0,

		clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,

				PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |

				PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |

				PMU_PPE_QSB | PMU_PPE_TOP);

		clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY);

		clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY);

		clkdev_add_pmu("1e108000.gswip", "gphy0", 0, 0, PMU_GPHY);

		clkdev_add_pmu("1e108000.gswip", "gphy1", 0, 0, PMU_GPHY);

		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);

		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);

		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);