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Commit cf700566 authored by Anson Huang's avatar Anson Huang Committed by Greg Kroah-Hartman
Browse files

ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D 



commit 4562fa4c86c92a2df635fe0697c9e06379738741 upstream.

ARM_ERRATA_814220 has below description:

The v7 ARM states that all cache and branch predictor maintenance
operations that do not specify an address execute, relative to
each other, in program order.
However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation.
This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
r0p4, r0p5.

i.MX6UL and i.MX7D have Cortex-A7 r0p5 inside, need to enable
ARM_ERRATA_814220 for proper workaround.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
Cc: Christian Eggers <ceggers@arri.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 4ac80b02

arch/arm/mach-imx/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -520,6 +520,7 @@ config SOC_IMX6UL 
	bool "i.MX6 UltraLite support"

	select PINCTRL_IMX6UL

	select SOC_IMX6

	select ARM_ERRATA_814220



	help

	  This enables support for Freescale i.MX6 UltraLite processor.
@@ -556,6 +557,7 @@ config SOC_IMX7D 
	select PINCTRL_IMX7D

	select SOC_IMX7D_CA7 if ARCH_MULTI_V7

	select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M

	select ARM_ERRATA_814220

	help

		This enables support for Freescale i.MX7 Dual processor.