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Commit ceefcbf0 authored by Tingwei Zhang's avatar Tingwei Zhang
Browse files

ARM: dts: msm: Add etm save/restore for Lahaina 

Add device tree node to support ETM register save/restore function
across power collapse.

Change-Id: I5febc6634dfc1712e884ccc609fc2a3834480bf8
parent 650d63d8

qcom/lahaina.dtsi

+88 −0
Original line number Diff line number Diff line
@@ -1002,6 +1002,94 @@ 
		qcom,rtb-size = <0x100000>;

	};



	jtag_mm0: jtagmm@7040000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7040000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	jtag_mm1: jtagmm@7140000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7140000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};



	jtag_mm2: jtagmm@7240000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7240000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};



	jtag_mm3: jtagmm@7340000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7340000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};



	jtag_mm4: jtagmm@7440000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7440000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU4>;

	};



	jtag_mm5: jtagmm@7540000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7540000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU5>;

	};



	jtag_mm6: jtagmm@7640000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7640000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU6>;

	};



	jtag_mm7: jtagmm@7740000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7740000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU7>;

	};



	qcom,rmtfs_sharedmem@0 {

		compatible = "qcom,sharedmem-uio";

		reg = <0x0 0x200000>;