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Commit cea165c3 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Wait for vblank in hsw_enable_ips() 



Now that the vblank wait is gone from intel_enable_primary_plane(),
hsw_enable_ips() needs to do the vblank wait itself.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 75f7f3ec

drivers/gpu/drm/i915/intel_display.c

+6 −6
Original line number Diff line number Diff line
@@ -3734,17 +3734,17 @@ static void intel_disable_planes(struct drm_crtc *crtc) 


void hsw_enable_ips(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (!crtc->config.ips_enabled)

		return;



	/* We can only enable IPS after we enable a plane and wait for a vblank.

	 * We guarantee that the plane is enabled by calling intel_enable_ips

	 * only after intel_enable_plane. And intel_enable_plane already waits

	 * for a vblank, so all we need to do here is to enable the IPS bit. */

	/* We can only enable IPS after we enable a plane and wait for a vblank */

	intel_wait_for_vblank(dev, crtc->pipe);



	assert_plane_enabled(dev_priv, crtc->plane);

	if (IS_BROADWELL(crtc->base.dev)) {

	if (IS_BROADWELL(dev)) {

		mutex_lock(&dev_priv->rps.hw_lock);

		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));

		mutex_unlock(&dev_priv->rps.hw_lock);

drivers/gpu/drm/i915/intel_sprite.c

+1 −4
Original line number Diff line number Diff line
@@ -696,10 +696,7 @@ intel_post_enable_primary(struct drm_crtc *crtc) 
	 * when going from primary only to sprite only and vice

	 * versa.

	 */

	if (intel_crtc->config.ips_enabled) {

		intel_wait_for_vblank(dev, intel_crtc->pipe);

	hsw_enable_ips(intel_crtc);

	}



	mutex_lock(&dev->struct_mutex);

	intel_update_fbc(dev);