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Commit ce91a923 authored by Naresh Kumar Inna's avatar Naresh Kumar Inna Committed by James Bottomley
Browse files

[SCSI] cxgb4/cxgb4vf: Chelsio FCoE offload driver submission (common header updates). 



This patch contains updates to firmware/hardware header files shared
between csiostor and cxgb4/cxgb4vf, and the resulting changes to the
cxgb4/cxgb4vf source files.

Signed-off-by: default avatarNaresh Kumar Inna <naresh@chelsio.com>
Cc: David Miller <davem@davemloft.net>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 53ad570b

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

+5 −5
Original line number Diff line number Diff line
@@ -3203,7 +3203,7 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 
	memset(c, 0, sizeof(*c));

	c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |

			       FW_CMD_REQUEST | FW_CMD_READ);

	c->retval_len16 = htonl(FW_LEN16(*c));

	c->cfvalid_to_len16 = htonl(FW_LEN16(*c));

	ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);

	if (ret < 0)

		return ret;
@@ -3397,7 +3397,7 @@ static int adap_init0_config(struct adapter *adapter, int reset) 
		htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |

		      FW_CMD_REQUEST |

		      FW_CMD_READ);

	caps_cmd.retval_len16 =

	caps_cmd.cfvalid_to_len16 =

		htonl(FW_CAPS_CONFIG_CMD_CFVALID |

		      FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |

		      FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
@@ -3422,7 +3422,7 @@ static int adap_init0_config(struct adapter *adapter, int reset) 
		htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |

		      FW_CMD_REQUEST |

		      FW_CMD_WRITE);

	caps_cmd.retval_len16 = htonl(FW_LEN16(caps_cmd));

	caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));

	ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),

			 NULL);

	if (ret < 0)
@@ -3497,7 +3497,7 @@ static int adap_init0_no_config(struct adapter *adapter, int reset) 
	memset(&caps_cmd, 0, sizeof(caps_cmd));

	caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |

				     FW_CMD_REQUEST | FW_CMD_READ);

	caps_cmd.retval_len16 = htonl(FW_LEN16(caps_cmd));

	caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));

	ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),

			 &caps_cmd);

	if (ret < 0)
@@ -3929,7 +3929,7 @@ static int adap_init0(struct adapter *adap) 
	memset(&caps_cmd, 0, sizeof(caps_cmd));

	caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |

				     FW_CMD_REQUEST | FW_CMD_READ);

	caps_cmd.retval_len16 = htonl(FW_LEN16(caps_cmd));

	caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));

	ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),

			 &caps_cmd);

	if (ret < 0)

drivers/net/ethernet/chelsio/cxgb4/sge.c

+3 −3
Original line number Diff line number Diff line
@@ -508,7 +508,7 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) 
{

	if (q->pend_cred >= 8) {

		wmb();

		t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO |

		t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO(1) |

			     QID(q->cntxt_id) | PIDX(q->pend_cred / 8));

		q->pend_cred &= 7;

	}
@@ -2082,10 +2082,10 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 
			goto fl_nomem;



		flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);

		c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN |

		c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN(1) |

					    FW_IQ_CMD_FL0FETCHRO(1) |

					    FW_IQ_CMD_FL0DATARO(1) |

					    FW_IQ_CMD_FL0PADEN);

					    FW_IQ_CMD_FL0PADEN(1));

		c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN(2) |

				FW_IQ_CMD_FL0FBMAX(3));

		c.fl0size = htons(flsz);

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

+10 −10
Original line number Diff line number Diff line
@@ -648,12 +648,12 @@ static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 


	if (!byte_cnt || byte_cnt > 4)

		return -EINVAL;

	if (t4_read_reg(adapter, SF_OP) & BUSY)

	if (t4_read_reg(adapter, SF_OP) & SF_BUSY)

		return -EBUSY;

	cont = cont ? SF_CONT : 0;

	lock = lock ? SF_LOCK : 0;

	t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));

	ret = t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5);

	ret = t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);

	if (!ret)

		*valp = t4_read_reg(adapter, SF_DATA);

	return ret;
@@ -676,14 +676,14 @@ static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 
{

	if (!byte_cnt || byte_cnt > 4)

		return -EINVAL;

	if (t4_read_reg(adapter, SF_OP) & BUSY)

	if (t4_read_reg(adapter, SF_OP) & SF_BUSY)

		return -EBUSY;

	cont = cont ? SF_CONT : 0;

	lock = lock ? SF_LOCK : 0;

	t4_write_reg(adapter, SF_DATA, val);

	t4_write_reg(adapter, SF_OP, lock |

		     cont | BYTECNT(byte_cnt - 1) | OP_WR);

	return t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5);

	return t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);

}



/**
@@ -2252,14 +2252,14 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 
		t4_write_reg(adap, EPIO_REG(DATA0), mask0);

		t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);

		t4_read_reg(adap, EPIO_REG(OP));                /* flush */

		if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY)

		if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)

			return -ETIMEDOUT;



		/* write CRC */

		t4_write_reg(adap, EPIO_REG(DATA0), crc);

		t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);

		t4_read_reg(adap, EPIO_REG(OP));                /* flush */

		if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY)

		if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)

			return -ETIMEDOUT;

	}

#undef EPIO_REG
@@ -2405,7 +2405,7 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 
retry:

	memset(&c, 0, sizeof(c));

	INIT_CMD(c, HELLO, WRITE);

	c.err_to_mbasyncnot = htonl(

	c.err_to_clearinit = htonl(

		FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |

		FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |

		FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
@@ -2426,7 +2426,7 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 
		return ret;

	}



	v = ntohl(c.err_to_mbasyncnot);

	v = ntohl(c.err_to_clearinit);

	master_mbox = FW_HELLO_CMD_MBMASTER_GET(v);

	if (state) {

		if (v & FW_HELLO_CMD_ERR)
@@ -2774,7 +2774,7 @@ int t4_fw_config_file(struct adapter *adap, unsigned int mbox, 
		htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |

		      FW_CMD_REQUEST |

		      FW_CMD_READ);

	caps_cmd.retval_len16 =

	caps_cmd.cfvalid_to_len16 =

		htonl(FW_CAPS_CONFIG_CMD_CFVALID |

		      FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |

		      FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
@@ -2797,7 +2797,7 @@ int t4_fw_config_file(struct adapter *adap, unsigned int mbox, 
		htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |

		      FW_CMD_REQUEST |

		      FW_CMD_WRITE);

	caps_cmd.retval_len16 = htonl(FW_LEN16(caps_cmd));

	caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));

	return t4_wr_mbox(adap, mbox, &caps_cmd, sizeof(caps_cmd), NULL);

}

drivers/net/ethernet/chelsio/cxgb4/t4_msg.h

+1 −0
Original line number Diff line number Diff line
@@ -658,6 +658,7 @@ struct ulptx_sgl { 
	__be32 cmd_nsge;

#define ULPTX_CMD(x) ((x) << 24)

#define ULPTX_NSGE(x) ((x) << 0)

#define ULPTX_MORE (1U << 23)

	__be32 len0;

	__be64 addr0;

	struct ulptx_sge_pair sge[0];

drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

+34 −2
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ 
#define  QID_MASK    0xffff8000U

#define  QID_SHIFT   15

#define  QID(x)      ((x) << QID_SHIFT)

#define  DBPRIO      0x00004000U

#define  DBPRIO(x)   ((x) << 14)

#define  PIDX_MASK   0x00003fffU

#define  PIDX_SHIFT  0

#define  PIDX(x)     ((x) << PIDX_SHIFT)
@@ -193,6 +193,12 @@ 
#define SGE_FL_BUFFER_SIZE1 0x1048

#define SGE_FL_BUFFER_SIZE2 0x104c

#define SGE_FL_BUFFER_SIZE3 0x1050

#define SGE_FL_BUFFER_SIZE4 0x1054

#define SGE_FL_BUFFER_SIZE5 0x1058

#define SGE_FL_BUFFER_SIZE6 0x105c

#define SGE_FL_BUFFER_SIZE7 0x1060

#define SGE_FL_BUFFER_SIZE8 0x1064



#define SGE_INGRESS_RX_THRESHOLD 0x10a0

#define  THRESHOLD_0_MASK   0x3f000000U

#define  THRESHOLD_0_SHIFT  24
@@ -217,6 +223,17 @@ 
#define  EGRTHRESHOLD(x)     ((x) << EGRTHRESHOLDshift)

#define  EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)



#define SGE_DBFIFO_STATUS 0x10a4

#define  HP_INT_THRESH_SHIFT 28

#define  HP_INT_THRESH_MASK  0xfU

#define  HP_INT_THRESH(x)    ((x) << HP_INT_THRESH_SHIFT)

#define  LP_INT_THRESH_SHIFT 12

#define  LP_INT_THRESH_MASK  0xfU

#define  LP_INT_THRESH(x)    ((x) << LP_INT_THRESH_SHIFT)



#define SGE_DOORBELL_CONTROL 0x10a8

#define  ENABLE_DROP        (1 << 13)



#define SGE_TIMER_VALUE_0_AND_1 0x10b8

#define  TIMERVALUE0_MASK   0xffff0000U

#define  TIMERVALUE0_SHIFT  16
@@ -277,6 +294,10 @@ 
#define A_SGE_CTXT_CMD 0x11fc

#define A_SGE_DBQ_CTXT_BADDR 0x1084



#define PCIE_PF_CFG 0x40

#define  AIVEC(x)	((x) << 4)

#define  AIVEC_MASK	0x3ffU



#define PCIE_PF_CLI 0x44

#define PCIE_INT_CAUSE 0x3004

#define  UNXSPLCPLERR  0x20000000U
@@ -322,6 +343,13 @@ 
#define PCIE_MEM_ACCESS_OFFSET 0x306c



#define PCIE_FW 0x30b8

#define  PCIE_FW_ERR		0x80000000U

#define  PCIE_FW_INIT		0x40000000U

#define  PCIE_FW_HALT		0x20000000U

#define  PCIE_FW_MASTER_VLD	0x00008000U

#define  PCIE_FW_MASTER(x)	((x) << 12)

#define  PCIE_FW_MASTER_MASK	0x7

#define  PCIE_FW_MASTER_GET(x)	(((x) >> 12) & PCIE_FW_MASTER_MASK)



#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908

#define  RNPP 0x80000000U
@@ -432,6 +460,9 @@ 
#define  MBOWNER(x)     ((x) << MBOWNER_SHIFT)

#define  MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)



#define CIM_PF_HOST_INT_ENABLE 0x288

#define  MBMSGRDYINTEN(x) ((x) << 19)



#define CIM_PF_HOST_INT_CAUSE 0x28c

#define  MBMSGRDYINT 0x00080000U
@@ -922,7 +953,7 @@ 


#define SF_DATA 0x193f8

#define SF_OP 0x193fc

#define  BUSY          0x80000000U

#define  SF_BUSY       0x80000000U

#define  SF_LOCK       0x00000010U

#define  SF_CONT       0x00000008U

#define  BYTECNT_MASK  0x00000006U
@@ -981,6 +1012,7 @@ 
#define  I2CM       0x00000002U

#define  CIM        0x00000001U



#define PL_INT_ENABLE 0x19410

#define PL_INT_MAP0 0x19414

#define PL_RST 0x19428

#define  PIORST     0x00000002U