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Commit ce55522c authored by Miquel Raynal's avatar Miquel Raynal Committed by Gregory CLEMENT
Browse files

arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes 



Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k
based boards.

The MacchiatoBin is a bit particular as the Armada8k-PCI IP supports
x4 link widths and in this case the PHY for each lane must be
referenced.

Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent 01d0deba

arch/arm64/boot/dts/marvell/armada-7040-db.dts

+2 −0
Original line number Diff line number Diff line
@@ -124,6 +124,8 @@ 


&cp0_pcie2 {

	status = "okay";

	phys = <&cp0_comphy5 2>;

	phy-names = "cp0-pcie2-x1-phy";

};



&cp0_i2c0 {

arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts

+2 −0
Original line number Diff line number Diff line
@@ -243,6 +243,8 @@ 
	pinctrl-names = "default";

	pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;

	reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;

	phys = <&cp0_comphy0 0>;

	phy-names = "cp0-pcie0-x1-phy";

	status = "okay";

};

arch/arm64/boot/dts/marvell/armada-8040-db.dts

+10 −0
Original line number Diff line number Diff line
@@ -108,11 +108,15 @@ 


/* CON6 on CP0 expansion */

&cp0_pcie0 {

	phys = <&cp0_comphy0 0>;

	phy-names = "cp0-pcie0-x1-phy";

	status = "okay";

};



/* CON5 on CP0 expansion */

&cp0_pcie2 {

	phys = <&cp0_comphy5 2>;

	phy-names = "cp0-pcie2-x1-phy";

	status = "okay";

};
@@ -198,16 +202,22 @@ 


/* CON6 on CP1 expansion */

&cp1_pcie0 {

	phys = <&cp1_comphy0 0>;

	phy-names = "cp1-pcie0-x1-phy";

	status = "okay";

};



/* CON7 on CP1 expansion */

&cp1_pcie1 {

	phys = <&cp1_comphy4 1>;

	phy-names = "cp1-pcie1-x1-phy";

	status = "okay";

};



/* CON5 on CP1 expansion */

&cp1_pcie2 {

	phys = <&cp1_comphy5 2>;

	phy-names = "cp1-pcie2-x1-phy";

	status = "okay";

};

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -186,6 +186,10 @@ 
	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;

	ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000

		  0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;

	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,

	       <&cp0_comphy2 0>, <&cp0_comphy3 0>;

	phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",

		    "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";

	status = "okay";

};