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Commit cdfdea07 authored by Andrey Smirnov's avatar Andrey Smirnov Committed by Shawn Guo
Browse files

arm64: dts: imx8mq-evk: Enable PCIE0 interface 



Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module.

Signed-off-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent fc26e600

arch/arm64/boot/dts/freescale/imx8mq-evk.dts

+42 −0
Original line number Diff line number Diff line
@@ -21,6 +21,12 @@ 
		reg = <0x00000000 0x40000000 0 0xc0000000>;

	};



	pcie0_refclk: pcie0-refclk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <100000000>;

	};



	reg_usdhc2_vmmc: regulator-vsd-3v3 {

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_reg_usdhc2>;
@@ -118,6 +124,17 @@ 
	status = "okay";

};



&gpio5 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_wifi_reset>;



	wl-reg-on {

		gpio-hog;

		gpios = <29 GPIO_ACTIVE_HIGH>;

		output-high;

	};

};



&i2c1 {

	clock-frequency = <100000>;

	pinctrl-names = "default";
@@ -209,6 +226,18 @@ 
	};

};



&pcie0 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,

		 <&clk IMX8MQ_CLK_PCIE1_AUX>,

		 <&clk IMX8MQ_CLK_PCIE1_PHY>,

		 <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

	status = "okay";

};



&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart1>;
@@ -303,6 +332,13 @@ 
		>;

	};



	pinctrl_pcie0: pcie0grp {

		fsl,pins = <

			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76

			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x16

		>;

	};



	pinctrl_qspi: qspigrp {

		fsl,pins = <

			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
@@ -430,4 +466,10 @@ 
			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6

		>;

	};



	pinctrl_wifi_reset: wifiresetgrp {

		fsl,pins = <

			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16

		>;

	};

};