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Commit cde274c0 authored by Mike Mason's avatar Mike Mason Committed by Benjamin Herrenschmidt
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powerpc/eeh: PERR/SERR bit settings during EEH device recovery 



The following patch restores the PERR and SERR bits in the PCI
command register during an EEH device recovery. We have found
at least one case (an Agilent test card) where the PERR/SERR
bits are set to 1 by firmware at boot time, but are not restored
to 1 during EEH recovery.  The patch fixes the Agilent card
problem.  It has been tested on several other EEH-enabled cards
with no regressions.

Signed-off-by: default avatarMike Mason <mmlnx@us.ibm.com>
Acked-by: default avatarLinas Vepstas <linasvepstas@gmail.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent b887ec62

arch/powerpc/platforms/pseries/eeh.c

+14 −0
Original line number Diff line number Diff line
@@ -812,6 +812,7 @@ int rtas_set_slot_reset(struct pci_dn *pdn) 
static inline void __restore_bars (struct pci_dn *pdn)

{

	int i;

	u32 cmd;



	if (NULL==pdn->phb) return;

	for (i=4; i<10; i++) {
@@ -832,6 +833,19 @@ static inline void __restore_bars (struct pci_dn *pdn) 


	/* max latency, min grant, interrupt pin and line */

	rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);



	/* Restore PERR & SERR bits, some devices require it,

	   don't touch the other command bits */

	rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);

	if (pdn->config_space[1] & PCI_COMMAND_PARITY)

		cmd |= PCI_COMMAND_PARITY;

	else

		cmd &= ~PCI_COMMAND_PARITY;

	if (pdn->config_space[1] & PCI_COMMAND_SERR)

		cmd |= PCI_COMMAND_SERR;

	else

		cmd &= ~PCI_COMMAND_SERR;

	rtas_write_config(pdn, PCI_COMMAND, 4, cmd);

}



/**