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Commit cd782f9d authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Mauro Carvalho Chehab
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[media] v4l: omap4iss: Fix operators precedence in ternary operators



The ternary operator ? : has a low precedence. Use parenthesis where
needed.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarMauro Carvalho Chehab <m.chehab@samsung.com>
parent 380df42b
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+7 −13
Original line number Diff line number Diff line
@@ -274,7 +274,7 @@ static void csi2_set_outaddr(struct iss_csi2_device *csi2, u32 addr)
 */
static inline int is_usr_def_mapping(u32 format_id)
{
	return ((format_id & 0xF0) == 0x40) ? 1 : 0;
	return (format_id & 0xF0) == 0x40 ? 1 : 0;
}

/*
@@ -766,16 +766,11 @@ void omap4iss_csi2_isr(struct iss_csi2_device *csi2)
			      CSI2_IRQ_FIFO_OVF)) {
		dev_dbg(iss->dev,
			"CSI2 Err: OCP:%d SHORT:%d ECC:%d CPXIO:%d OVF:%d\n",
			(csi2_irqstatus &
			 CSI2_IRQ_OCP_ERR) ? 1 : 0,
			(csi2_irqstatus &
			 CSI2_IRQ_SHORT_PACKET) ? 1 : 0,
			(csi2_irqstatus &
			 CSI2_IRQ_ECC_NO_CORRECTION) ? 1 : 0,
			(csi2_irqstatus &
			 CSI2_IRQ_COMPLEXIO_ERR) ? 1 : 0,
			(csi2_irqstatus &
			 CSI2_IRQ_FIFO_OVF) ? 1 : 0);
			csi2_irqstatus & CSI2_IRQ_OCP_ERR ? 1 : 0,
			csi2_irqstatus & CSI2_IRQ_SHORT_PACKET ? 1 : 0,
			csi2_irqstatus & CSI2_IRQ_ECC_NO_CORRECTION ? 1 : 0,
			csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR ? 1 : 0,
			csi2_irqstatus & CSI2_IRQ_FIFO_OVF ? 1 : 0);
		pipe->error = true;
	}

@@ -1209,8 +1204,7 @@ static int csi2_link_setup(struct media_entity *entity,
		return -EINVAL;
	}

	ctrl->vp_only_enable =
		(csi2->output & CSI2_OUTPUT_MEMORY) ? false : true;
	ctrl->vp_only_enable = csi2->output & CSI2_OUTPUT_MEMORY ? false : true;
	ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_IPIPEIF);

	return 0;
+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ static void ipipe_enable(struct iss_ipipe_device *ipipe, u8 enable)

	writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_EN) &
		~IPIPE_SRC_EN_EN) |
		enable ? IPIPE_SRC_EN_EN : 0,
		(enable ? IPIPE_SRC_EN_EN : 0),
		iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_EN);
}

+2 −2
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ static void ipipeif_write_enable(struct iss_ipipeif_device *ipipeif, u8 enable)

	writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN) &
		~ISIF_SYNCEN_DWEN) |
		enable ? ISIF_SYNCEN_DWEN : 0,
		(enable ? ISIF_SYNCEN_DWEN : 0),
		iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN);
}

@@ -100,7 +100,7 @@ static void ipipeif_enable(struct iss_ipipeif_device *ipipeif, u8 enable)

	writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN) &
		~ISIF_SYNCEN_SYEN) |
		enable ? ISIF_SYNCEN_SYEN : 0,
		(enable ? ISIF_SYNCEN_SYEN : 0),
		iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN);
}

+5 −7
Original line number Diff line number Diff line
@@ -118,13 +118,13 @@ static void resizer_enable(struct iss_resizer_device *resizer, u8 enable)

	writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_EN) &
		~RSZ_SRC_EN_SRC_EN) |
		enable ? RSZ_SRC_EN_SRC_EN : 0,
		(enable ? RSZ_SRC_EN_SRC_EN : 0),
		iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_EN);

	/* TODO: Enable RSZB */
	writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN) &
		~RSZ_EN_EN) |
		enable ? RSZ_EN_EN : 0,
		(enable ? RSZ_EN_EN : 0),
		iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN);
}

@@ -202,7 +202,7 @@ static void resizer_configure(struct iss_resizer_device *resizer)
	/* Select RSZ input */
	writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0) &
		~RSZ_SRC_FMT0_SEL) |
		(resizer->input == RESIZER_INPUT_IPIPEIF) ? RSZ_SRC_FMT0_SEL : 0,
		(resizer->input == RESIZER_INPUT_IPIPEIF ? RSZ_SRC_FMT0_SEL : 0),
		iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0);

	/* RSZ ignores WEN signal from IPIPE/IPIPEIF */
@@ -318,10 +318,8 @@ void omap4iss_resizer_isr(struct iss_resizer_device *resizer, u32 events)
	if (events & (ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR |
		      ISP5_IRQ_RSZ_FIFO_OVF)) {
		dev_dbg(iss->dev, "RSZ Err: FIFO_IN_BLK:%d, FIFO_OVF:%d\n",
			(events &
			 ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR) ? 1 : 0,
			(events &
			 ISP5_IRQ_RSZ_FIFO_OVF) ? 1 : 0);
			events & ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR ? 1 : 0,
			events & ISP5_IRQ_RSZ_FIFO_OVF ? 1 : 0);
		pipe->error = true;
	}