Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cd664078 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

drm/i915: disable LVDS clock gating on CPT v2 



Needed to prevent display corruption in high res panels.

v2: use correct unit names (Rodrigo)

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: default avatarUlrich Drepper <drepper@gmail.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 61e6cfa8

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -4279,7 +4279,9 @@ 
#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)



#define SOUTH_DSPCLK_GATE_D	0xc2020

#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)

#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)

#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)

#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)



/* CPU: FDI_TX */

drivers/gpu/drm/i915/intel_pm.c

+3 −1
Original line number Diff line number Diff line
@@ -4759,7 +4759,9 @@ static void cpt_init_clock_gating(struct drm_device *dev) 
	 * gating for the panel power sequencer or it will fail to

	 * start up when no ports are active.

	 */

	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |

		   PCH_DPLUNIT_CLOCK_GATE_DISABLE |

		   PCH_CPUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |

		   DPLS_EDP_PPS_FIX_DIS);

	/* The below fixes the weird display corruption, a few pixels shifted