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Unverified Commit cd54074e authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
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drm/sun4i: Not all DW HDMI controllers has scrambled addresses 



Currently supported Allwinner SoCs with DW HDMI controller have
scrambled addresses and read lock. However, that is not true in general.
For example, A80 and H6 have normal addresses and normal read access.

Move code for unscrambling addresses and unlocking read access to it's
own function and call it from init function.

Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-16-jernej.skrabec@siol.net
parent c8c78ac2

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

+15 −8
Original line number Diff line number Diff line
@@ -279,8 +279,21 @@ static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = { 
	.setup_hpd = &dw_hdmi_phy_setup_hpd,

};



static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)

{

	/* enable read access to HDMI controller */

	regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,

		     SUN8I_HDMI_PHY_READ_EN_MAGIC);



	/* unscramble register offsets */

	regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,

		     SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);

}



static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy)

{

	sun8i_hdmi_phy_unlock(phy);



	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,

			   SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,

			   SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);
@@ -298,6 +311,8 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) 
{

	unsigned int val;



	sun8i_hdmi_phy_unlock(phy);



	regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0);

	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,

			   SUN8I_HDMI_PHY_ANA_CFG1_ENBI,
@@ -372,14 +387,6 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) 


void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)

{

	/* enable read access to HDMI controller */

	regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,

		     SUN8I_HDMI_PHY_READ_EN_MAGIC);



	/* unscramble register offsets */

	regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,

		     SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);



	phy->variant->phy_init(phy);

}