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Commit cd414f3d authored by Jordan Crouse's avatar Jordan Crouse Committed by Rob Clark
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drm/msm: Move memptrs to msm_gpu 



When we move to multiple ringbuffers we're going to store the data
in the memptrs on a per-ring basis. In order to prepare for that
move the current memptrs from the adreno namespace into msm_gpu.
This is way cleaner and immediately lets us kill off some sub
functions so there is much less cost later when we do move to
per-ring structs.

Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent f7de1545

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+0 −1
Original line number Diff line number Diff line
@@ -444,7 +444,6 @@ static const struct adreno_gpu_funcs funcs = { 
		.pm_suspend = msm_gpu_pm_suspend,

		.pm_resume = msm_gpu_pm_resume,

		.recover = a3xx_recover,

		.last_fence = adreno_last_fence,

		.submit = adreno_submit,

		.flush = adreno_flush,

		.irq = a3xx_irq,

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+0 −1
Original line number Diff line number Diff line
@@ -532,7 +532,6 @@ static const struct adreno_gpu_funcs funcs = { 
		.pm_suspend = a4xx_pm_suspend,

		.pm_resume = a4xx_pm_resume,

		.recover = a4xx_recover,

		.last_fence = adreno_last_fence,

		.submit = adreno_submit,

		.flush = adreno_flush,

		.irq = a4xx_irq,

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+3 −5
Original line number Diff line number Diff line
@@ -116,7 +116,6 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname) 
static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

	struct msm_file_private *ctx)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	struct msm_drm_private *priv = gpu->dev->dev_private;

	struct msm_ringbuffer *ring = gpu->rb;

	unsigned int i, ibs = 0;
@@ -143,8 +142,8 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 


	OUT_PKT7(ring, CP_EVENT_WRITE, 4);

	OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31));

	OUT_RING(ring, lower_32_bits(rbmemptr(adreno_gpu, fence)));

	OUT_RING(ring, upper_32_bits(rbmemptr(adreno_gpu, fence)));

	OUT_RING(ring, lower_32_bits(rbmemptr(gpu, fence)));

	OUT_RING(ring, upper_32_bits(rbmemptr(gpu, fence)));

	OUT_RING(ring, submit->fence->seqno);



	gpu->funcs->flush(gpu);
@@ -821,7 +820,7 @@ static void a5xx_fault_detect_irq(struct msm_gpu *gpu) 
	struct msm_drm_private *priv = dev->dev_private;



	dev_err(dev->dev, "gpu fault fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",

		gpu->funcs->last_fence(gpu),

		gpu->memptrs->fence,

		gpu_read(gpu, REG_A5XX_RBBM_STATUS),

		gpu_read(gpu, REG_A5XX_CP_RB_RPTR),

		gpu_read(gpu, REG_A5XX_CP_RB_WPTR),
@@ -1009,7 +1008,6 @@ static const struct adreno_gpu_funcs funcs = { 
		.pm_suspend = a5xx_pm_suspend,

		.pm_resume = a5xx_pm_resume,

		.recover = a5xx_recover,

		.last_fence = adreno_last_fence,

		.submit = a5xx_submit,

		.flush = adreno_flush,

		.irq = a5xx_irq,

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+12 −43
Original line number Diff line number Diff line
@@ -182,8 +182,8 @@ int adreno_hw_init(struct msm_gpu *gpu) 
	gpu->rb->cur = gpu->rb->start;



	/* reset completed fence seqno: */

	adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;

	adreno_gpu->memptrs->rptr  = 0;

	gpu->memptrs->fence = gpu->fctx->completed_fence;

	gpu->memptrs->rptr  = 0;



	/* Setup REG_CP_RB_CNTL: */

	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
@@ -198,8 +198,7 @@ int adreno_hw_init(struct msm_gpu *gpu) 


	if (!adreno_is_a430(adreno_gpu)) {

		adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,

			REG_ADRENO_CP_RB_RPTR_ADDR_HI,

			rbmemptr(adreno_gpu, rptr));

			REG_ADRENO_CP_RB_RPTR_ADDR_HI, rbmemptr(gpu, rptr));

	}



	return 0;
@@ -213,17 +212,13 @@ static uint32_t get_wptr(struct msm_ringbuffer *ring) 
/* Use this helper to read rptr, since a430 doesn't update rptr in memory */

static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)

{

	struct msm_gpu *gpu = &adreno_gpu->base;



	if (adreno_is_a430(adreno_gpu))

		return adreno_gpu->memptrs->rptr = adreno_gpu_read(

		return gpu->memptrs->rptr = adreno_gpu_read(

			adreno_gpu, REG_ADRENO_CP_RB_RPTR);

	else

		return adreno_gpu->memptrs->rptr;

}



uint32_t adreno_last_fence(struct msm_gpu *gpu)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	return adreno_gpu->memptrs->fence;

		return gpu->memptrs->rptr;

}



void adreno_recover(struct msm_gpu *gpu)
@@ -288,7 +283,7 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 


	OUT_PKT3(ring, CP_EVENT_WRITE, 3);

	OUT_RING(ring, CACHE_FLUSH_TS);

	OUT_RING(ring, rbmemptr(adreno_gpu, fence));

	OUT_RING(ring, rbmemptr(gpu, fence));

	OUT_RING(ring, submit->fence->seqno);



	/* we could maybe be clever and only CP_COND_EXEC the interrupt: */
@@ -361,7 +356,7 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m) 
			adreno_gpu->rev.major, adreno_gpu->rev.minor,

			adreno_gpu->rev.patchid);



	seq_printf(m, "fence:    %d/%d\n", adreno_gpu->memptrs->fence,

	seq_printf(m, "fence:    %d/%d\n", gpu->memptrs->fence,

			gpu->fctx->last_fence);

	seq_printf(m, "rptr:     %d\n", get_rptr(adreno_gpu));

	seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));
@@ -396,7 +391,7 @@ void adreno_dump_info(struct msm_gpu *gpu) 
			adreno_gpu->rev.major, adreno_gpu->rev.minor,

			adreno_gpu->rev.patchid);



	printk("fence:    %d/%d\n", adreno_gpu->memptrs->fence,

	printk("fence:    %d/%d\n", gpu->memptrs->fence,

			gpu->fctx->last_fence);

	printk("rptr:     %d\n", get_rptr(adreno_gpu));

	printk("rb wptr:  %d\n", get_wptr(gpu->rb));
@@ -443,7 +438,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 
	struct adreno_platform_config *config = pdev->dev.platform_data;

	struct msm_gpu_config adreno_gpu_config  = { 0 };

	struct msm_gpu *gpu = &adreno_gpu->base;

	int ret;



	adreno_gpu->funcs = funcs;

	adreno_gpu->info = adreno_info(config->rev);
@@ -472,39 +466,14 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 
	pm_runtime_use_autosuspend(&pdev->dev);

	pm_runtime_enable(&pdev->dev);



	ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,

	return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,

			adreno_gpu->info->name, &adreno_gpu_config);

	if (ret)

		return ret;



	adreno_gpu->memptrs = msm_gem_kernel_new(drm,

		sizeof(*adreno_gpu->memptrs), MSM_BO_UNCACHED, gpu->aspace,

		&adreno_gpu->memptrs_bo, &adreno_gpu->memptrs_iova);



	if (IS_ERR(adreno_gpu->memptrs)) {

		ret = PTR_ERR(adreno_gpu->memptrs);

		adreno_gpu->memptrs = NULL;

		dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);

	}



	return ret;

}



void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)

{

	struct msm_gpu *gpu = &adreno_gpu->base;



	if (adreno_gpu->memptrs_bo) {

		if (adreno_gpu->memptrs)

			msm_gem_put_vaddr(adreno_gpu->memptrs_bo);



		if (adreno_gpu->memptrs_iova)

			msm_gem_put_iova(adreno_gpu->memptrs_bo, gpu->aspace);



		drm_gem_object_unreference_unlocked(adreno_gpu->memptrs_bo);

	}

	release_firmware(adreno_gpu->pm4);

	release_firmware(adreno_gpu->pfp);



	msm_gpu_cleanup(gpu);

	msm_gpu_cleanup(&adreno_gpu->base);

}

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+0 −16
Original line number Diff line number Diff line
@@ -82,14 +82,6 @@ struct adreno_info { 


const struct adreno_info *adreno_info(struct adreno_rev rev);



#define rbmemptr(adreno_gpu, member)  \

	((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))



struct adreno_rbmemptrs {

	volatile uint32_t rptr;

	volatile uint32_t fence;

};



struct adreno_gpu {

	struct msm_gpu base;

	struct adreno_rev rev;
@@ -125,13 +117,6 @@ struct adreno_gpu { 
	/* firmware: */

	const struct firmware *pm4, *pfp;



	/* ringbuffer rptr/wptr: */

	// TODO should this be in msm_ringbuffer?  I think it would be

	// different for z180..

	struct adreno_rbmemptrs *memptrs;

	struct drm_gem_object *memptrs_bo;

	uint64_t memptrs_iova;



	/*

	 * Register offsets are different between some GPUs.

	 * GPU specific offsets will be exported by GPU specific
@@ -220,7 +205,6 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 
const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,

		const char *fwname);

int adreno_hw_init(struct msm_gpu *gpu);

uint32_t adreno_last_fence(struct msm_gpu *gpu);

void adreno_recover(struct msm_gpu *gpu);

void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

		struct msm_file_private *ctx);