Loading qcom/shima.dtsi +2 −4 Original line number Diff line number Diff line Loading @@ -930,10 +930,8 @@ reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; Loading Loading
qcom/shima.dtsi +2 −4 Original line number Diff line number Diff line Loading @@ -930,10 +930,8 @@ reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; Loading