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Commit cd2e264d authored by Urvashi Agrawal's avatar Urvashi Agrawal Committed by Jordan Crouse
Browse files

msm: kgsl: Initialize CP engine before loading the zap shader 



If CP is not initialized and zap shader loading fails the GMU IFPC state
machine is uninitialized which causes unwanted mess. Reverse the order
of CP_INIT and zap to handle the situation gracefully.

Change-Id: I062e4c7febd8ee11099bae1b58c579851a43e8bd
Signed-off-by: default avatarUrvashi Agrawal <urvaagra@codeaurora.org>
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 8e842076

drivers/gpu/msm/adreno_a6xx.c

+16 −28
Original line number Diff line number Diff line
@@ -646,27 +646,6 @@ void a6xx_start(struct adreno_device *adreno_dev) 
	}

}



/*

 * a6xx_microcode_load() - Load microcode

 * @adreno_dev: Pointer to adreno device

 */

static int a6xx_microcode_load(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_firmware *fw = ADRENO_FW(adreno_dev, ADRENO_FW_SQE);

	const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);

	uint64_t gpuaddr;



	gpuaddr = fw->memdesc->gpuaddr;

	kgsl_regwrite(device, A6XX_CP_SQE_INSTR_BASE_LO,

				lower_32_bits(gpuaddr));

	kgsl_regwrite(device, A6XX_CP_SQE_INSTR_BASE_HI,

				upper_32_bits(gpuaddr));



	return adreno_zap_shader_load(adreno_dev, a6xx_core->zap_name);

}





/*

 * CP_INIT_MAX_CONTEXT bit tells if the multiple hardware contexts can

 * be used at once of if they should be serialized
@@ -862,6 +841,8 @@ static int a6xx_post_start(struct adreno_device *adreno_dev) 


int a6xx_rb_start(struct adreno_device *adreno_dev)

{

	const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);

	struct adreno_firmware *fw = ADRENO_FW(adreno_dev, ADRENO_FW_SQE);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_ringbuffer *rb;

	uint64_t addr;
@@ -900,9 +881,12 @@ int a6xx_rb_start(struct adreno_device *adreno_dev) 
	kgsl_regwrite(device, A6XX_CP_RB_BASE_HI,

		upper_32_bits(rb->buffer_desc->gpuaddr));



	ret = a6xx_microcode_load(adreno_dev);

	if (ret)

		return ret;

	/* Program the ucode base for CP */

	kgsl_regwrite(device, A6XX_CP_SQE_INSTR_BASE_LO,

			lower_32_bits(fw->memdesc->gpuaddr));



	kgsl_regwrite(device, A6XX_CP_SQE_INSTR_BASE_HI,

			upper_32_bits(fw->memdesc->gpuaddr));



	/* Clear the SQE_HALT to start the CP engine */

	kgsl_regwrite(device, A6XX_CP_SQE_CNTL, 1);
@@ -911,17 +895,21 @@ int a6xx_rb_start(struct adreno_device *adreno_dev) 
	if (ret)

		return ret;



	ret = adreno_zap_shader_load(adreno_dev, a6xx_core->zap_name);

	if (ret)

		return ret;



	/*

	 * Take the GPU out of secure mode. Try the zap shader if it is loaded,

	 * otherwise just try to write directly to the secure control register

	 */

	if (!adreno_dev->zap_loaded)

		kgsl_regwrite(device, A6XX_RBBM_SECVID_TRUST_CNTL, 0);

	else

	else {

		ret = adreno_switch_to_unsecure_mode(adreno_dev, rb);



		if (ret)

			return ret;

	}



	return a6xx_post_start(adreno_dev);

}