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Commit cd1d3ee9 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Use intel_ types more consistently for watermark code (v2) 



Try to be more consistent about intel_* types rather than drm_* types
for lower-level driver functions.

v2:
 - Also drop the intel_crtc parameter from compute_intermediate_wm()
   since we can just extract it from the crtc_state parameter. (Ville)

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181210215415.19854-1-matthew.d.roper@intel.com
parent 0b5b45a6

drivers/gpu/drm/i915/i915_drv.h

+2 −4
Original line number Diff line number Diff line
@@ -281,16 +281,14 @@ struct drm_i915_display_funcs { 
	int (*get_fifo_size)(struct drm_i915_private *dev_priv,

			     enum i9xx_plane_id i9xx_plane);

	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);

	int (*compute_intermediate_wm)(struct drm_device *dev,

				       struct intel_crtc *intel_crtc,

				       struct intel_crtc_state *newstate);

	int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);

	void (*initial_watermarks)(struct intel_atomic_state *state,

				   struct intel_crtc_state *cstate);

	void (*atomic_update_watermarks)(struct intel_atomic_state *state,

					 struct intel_crtc_state *cstate);

	void (*optimize_watermarks)(struct intel_atomic_state *state,

				    struct intel_crtc_state *cstate);

	int (*compute_global_watermarks)(struct drm_atomic_state *state);

	int (*compute_global_watermarks)(struct intel_atomic_state *state);

	void (*update_wm)(struct intel_crtc *crtc);

	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);

	/* Returns the active state of the crtc, and if the crtc is active,

drivers/gpu/drm/i915/intel_display.c

+14 −19
Original line number Diff line number Diff line
@@ -10661,12 +10661,9 @@ static void intel_crtc_destroy(struct drm_crtc *crtc) 
 *

 * Returns true or false.

 */

static bool intel_wm_need_update(struct drm_plane *plane,

				 struct drm_plane_state *state)

static bool intel_wm_need_update(struct intel_plane_state *cur,

				 struct intel_plane_state *new)

{

	struct intel_plane_state *new = to_intel_plane_state(state);

	struct intel_plane_state *cur = to_intel_plane_state(plane->state);



	/* Update watermarks on tiling or size changes. */

	if (new->base.visible != cur->base.visible)

		return true;
@@ -10775,7 +10772,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat 
		/* must disable cxsr around plane enable/disable */

		if (plane->id != PLANE_CURSOR)

			pipe_config->disable_cxsr = true;

	} else if (intel_wm_need_update(&plane->base, plane_state)) {

	} else if (intel_wm_need_update(to_intel_plane_state(plane->base.state),

					to_intel_plane_state(plane_state))) {

		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {

			/* FIXME bollocks */

			pipe_config->update_wm_pre = true;
@@ -10954,8 +10952,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 
static int intel_crtc_atomic_check(struct drm_crtc *crtc,

				   struct drm_crtc_state *crtc_state)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(crtc->dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc_state *pipe_config =

		to_intel_crtc_state(crtc_state);
@@ -11004,9 +11001,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, 
		 * old state and the new state.  We can program these

		 * immediately.

		 */

		ret = dev_priv->display.compute_intermediate_wm(dev,

								intel_crtc,

								pipe_config);

		ret = dev_priv->display.compute_intermediate_wm(pipe_config);

		if (ret) {

			DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");

			return ret;
@@ -11964,7 +11959,7 @@ static void verify_wm_state(struct drm_crtc *crtc, 
	if (INTEL_GEN(dev_priv) < 9 || !new_state->active)

		return;



	skl_pipe_wm_get_hw_state(crtc, &hw_wm);

	skl_pipe_wm_get_hw_state(intel_crtc, &hw_wm);

	sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;



	skl_pipe_ddb_get_hw_state(intel_crtc, hw_ddb_y, hw_ddb_uv);
@@ -12619,9 +12614,9 @@ static int intel_modeset_checks(struct drm_atomic_state *state) 
 * phase.  The code here should be run after the per-crtc and per-plane 'check'

 * handlers to ensure that all derived state has been updated.

 */

static int calc_watermark_data(struct drm_atomic_state *state)

static int calc_watermark_data(struct intel_atomic_state *state)

{

	struct drm_device *dev = state->dev;

	struct drm_device *dev = state->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);



	/* Is there platform-specific watermark information to calculate? */
@@ -12713,7 +12708,7 @@ static int intel_atomic_check(struct drm_device *dev, 
		return ret;



	intel_fbc_choose_crtc(dev_priv, intel_state);

	return calc_watermark_data(state);

	return calc_watermark_data(intel_state);

}



static int intel_atomic_prepare_commit(struct drm_device *dev,
@@ -15843,15 +15838,15 @@ intel_modeset_setup_hw_state(struct drm_device *dev, 
	}



	if (IS_G4X(dev_priv)) {

		g4x_wm_get_hw_state(dev);

		g4x_wm_get_hw_state(dev_priv);

		g4x_wm_sanitize(dev_priv);

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		vlv_wm_get_hw_state(dev);

		vlv_wm_get_hw_state(dev_priv);

		vlv_wm_sanitize(dev_priv);

	} else if (INTEL_GEN(dev_priv) >= 9) {

		skl_wm_get_hw_state(dev);

		skl_wm_get_hw_state(dev_priv);

	} else if (HAS_PCH_SPLIT(dev_priv)) {

		ilk_wm_get_hw_state(dev);

		ilk_wm_get_hw_state(dev_priv);

	}



	for_each_intel_crtc(dev, crtc) {

drivers/gpu/drm/i915/intel_drv.h

+5 −5
Original line number Diff line number Diff line
@@ -2200,16 +2200,16 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv); 
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);

void gen6_rps_idle(struct drm_i915_private *dev_priv);

void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);

void g4x_wm_get_hw_state(struct drm_device *dev);

void vlv_wm_get_hw_state(struct drm_device *dev);

void ilk_wm_get_hw_state(struct drm_device *dev);

void skl_wm_get_hw_state(struct drm_device *dev);

void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);

void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);

void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);

void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);

void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,

			       struct skl_ddb_entry *ddb_y,

			       struct skl_ddb_entry *ddb_uv);

void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,

			  struct skl_ddb_allocation *ddb /* out */);

void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,

void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,

			      struct skl_pipe_wm *out);

void g4x_wm_sanitize(struct drm_i915_private *dev_priv);

void vlv_wm_sanitize(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_pm.c

+116 −139

File changed.

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