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Commit cc10ad25 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Paul Burton:

 - kexec support for the generic MIPS platform when running on a CPU
   including the MIPS Coherence Manager & related hardware.

 - Improvements to the definition of memory barriers used around MMIO
   accesses, and fixes in their use.

 - Switch to CONFIG_NO_BOOTMEM from Mike Rapoport, finally dropping
   reliance on the old bootmem code.

 - A number of fixes & improvements for Loongson 3 systems.

 - DT & config updates for the Microsemi Ocelot platform.

 - Workaround to enable USB power on the Netgear WNDR3400v3.

 - Various cleanups & fixes.

* tag 'mips_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (51 commits)
  MIPS: Cleanup DSP ASE detection
  MIPS: dts: Change upper case to lower case
  MIPS: generic: Add Network, SPI and I2C to ocelot_defconfig
  MIPS: Loongson-3: Fix BRIDGE irq delivery problem
  MIPS: Loongson-3: Fix CPU UART irq delivery problem
  MIPS: Remove unused PREF, PREFE & PREFX macros
  MIPS: lib: Use kernel_pref & user_pref in memcpy()
  MIPS: Remove unused CAT macro
  MIPS: Add kernel_pref & user_pref helpers
  MIPS: Remove unused TTABLE macro
  MIPS: Remove unused PIC macros
  MIPS: Remove unused MOVN & MOVZ macros
  MIPS: Provide actually relaxed MMIO accessors
  MIPS: Enforce strong ordering for MMIO accessors
  MIPS: Correct `mmiowb' barrier for `wbflush' platforms
  MIPS: Define MMIO ordering barriers
  MIPS: mscc: add PCB120 to the ocelot fitImage
  MIPS: mscc: add DT for Ocelot PCB120
  MIPS: memset: Limit excessive `noreorder' assembly mode use
  MIPS: memset: Fix CPU_DADDI_WORKAROUNDS `small_fixup' regression
  ...
parents ec9c1664 edbb4233

arch/mips/Kconfig

+39 −3
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ config MIPS 
	select GENERIC_CLOCKEVENTS

	select GENERIC_CMOS_UPDATE

	select GENERIC_CPU_AUTOPROBE

	select GENERIC_IOMAP

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

	select GENERIC_LIB_ASHLDI3
@@ -28,7 +29,6 @@ config MIPS 
	select GENERIC_LIB_CMPDI2

	select GENERIC_LIB_LSHRDI3

	select GENERIC_LIB_UCMPDI2

	select GENERIC_PCI_IOMAP

	select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC

	select GENERIC_SMP_IDLE_THREAD

	select GENERIC_TIME_VSYSCALL
@@ -78,6 +78,7 @@ config MIPS 
	select RTC_LIB if !MACH_LOONGSON64

	select SYSCTL_EXCEPTION_TRACE

	select VIRT_TO_BUS

	select NO_BOOTMEM



menu "Machine selection"
@@ -132,6 +133,7 @@ config MIPS_GENERIC 
	select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN

	select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN

	select USE_OF

	select UHI_BOOT

	help

	  Select this to build a kernel which aims to support multiple boards,

	  generally using a flattened device tree passed from the bootloader
@@ -1149,6 +1151,7 @@ config NO_IOPORT_MAP 


config GENERIC_CSUM

	bool

	default y if !CPU_HAS_LOAD_STORE_LR



config GENERIC_ISA_DMA

	bool
@@ -1367,6 +1370,7 @@ config CPU_LOONGSON3 
	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_HUGEPAGES

	select CPU_HAS_LOAD_STORE_LR

	select WEAK_ORDERING

	select WEAK_REORDERING_BEYOND_LLSC

	select MIPS_PGD_C0_CONTEXT
@@ -1443,6 +1447,7 @@ config CPU_MIPS32_R1 
	bool "MIPS32 Release 1"

	depends on SYS_HAS_CPU_MIPS32_R1

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	help
@@ -1460,6 +1465,7 @@ config CPU_MIPS32_R2 
	bool "MIPS32 Release 2"

	depends on SYS_HAS_CPU_MIPS32_R2

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_MSA
@@ -1478,7 +1484,6 @@ config CPU_MIPS32_R6 
	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_MSA

	select GENERIC_CSUM

	select HAVE_KVM

	select MIPS_O32_FP64_SUPPORT

	help
@@ -1491,6 +1496,7 @@ config CPU_MIPS64_R1 
	bool "MIPS64 Release 1"

	depends on SYS_HAS_CPU_MIPS64_R1

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM
@@ -1510,6 +1516,7 @@ config CPU_MIPS64_R2 
	bool "MIPS64 Release 2"

	depends on SYS_HAS_CPU_MIPS64_R2

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM
@@ -1531,7 +1538,6 @@ config CPU_MIPS64_R6 
	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_MSA

	select GENERIC_CSUM

	select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32

	select HAVE_KVM

	help
@@ -1544,6 +1550,7 @@ config CPU_R3000 
	bool "R3000"

	depends on SYS_HAS_CPU_R3000

	select CPU_HAS_WB

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	help
@@ -1558,12 +1565,14 @@ config CPU_TX39XX 
	bool "R39XX"

	depends on SYS_HAS_CPU_TX39XX

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_HAS_LOAD_STORE_LR



config CPU_VR41XX

	bool "R41xx"

	depends on SYS_HAS_CPU_VR41XX

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_HAS_LOAD_STORE_LR

	help

	  The options selects support for the NEC VR4100 series of processors.

	  Only choose this option if you have one of these processors as a
@@ -1575,6 +1584,7 @@ config CPU_R4300 
	depends on SYS_HAS_CPU_R4300

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_HAS_LOAD_STORE_LR

	help

	  MIPS Technologies R4300-series processors.
@@ -1584,6 +1594,7 @@ config CPU_R4X00 
	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HUGEPAGES

	select CPU_HAS_LOAD_STORE_LR

	help

	  MIPS Technologies R4000-series processors other than 4300, including

	  the R4000, R4400, R4600, and 4700.
@@ -1592,6 +1603,7 @@ config CPU_TX49XX 
	bool "R49XX"

	depends on SYS_HAS_CPU_TX49XX

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HUGEPAGES
@@ -1602,6 +1614,7 @@ config CPU_R5000 
	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HUGEPAGES

	select CPU_HAS_LOAD_STORE_LR

	help

	  MIPS Technologies R5000-series processors other than the Nevada.
@@ -1611,6 +1624,7 @@ config CPU_R5432 
	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HUGEPAGES

	select CPU_HAS_LOAD_STORE_LR



config CPU_R5500

	bool "R5500"
@@ -1618,6 +1632,7 @@ config CPU_R5500 
	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HUGEPAGES

	select CPU_HAS_LOAD_STORE_LR

	help

	  NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV

	  instruction set.
@@ -1628,6 +1643,7 @@ config CPU_NEVADA 
	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HUGEPAGES

	select CPU_HAS_LOAD_STORE_LR

	help

	  QED / PMC-Sierra RM52xx-series ("Nevada") processors.
@@ -1635,6 +1651,7 @@ config CPU_R8000 
	bool "R8000"

	depends on SYS_HAS_CPU_R8000

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_64BIT_KERNEL

	help

	  MIPS Technologies R8000 processors.  Note these processors are
@@ -1644,6 +1661,7 @@ config CPU_R10000 
	bool "R10000"

	depends on SYS_HAS_CPU_R10000

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM
@@ -1655,6 +1673,7 @@ config CPU_RM7000 
	bool "RM7000"

	depends on SYS_HAS_CPU_RM7000

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM
@@ -1663,6 +1682,7 @@ config CPU_RM7000 
config CPU_SB1

	bool "SB1"

	depends on SYS_HAS_CPU_SB1

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM
@@ -1673,6 +1693,7 @@ config CPU_CAVIUM_OCTEON 
	bool "Cavium Octeon processor"

	depends on SYS_HAS_CPU_CAVIUM_OCTEON

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_64BIT_KERNEL

	select WEAK_ORDERING

	select CPU_SUPPORTS_HIGHMEM
@@ -1702,6 +1723,7 @@ config CPU_BMIPS 
	select WEAK_ORDERING

	select CPU_SUPPORTS_HIGHMEM

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_CPUFREQ

	select MIPS_EXTERNAL_TIMER

	help
@@ -1710,6 +1732,7 @@ config CPU_BMIPS 
config CPU_XLR

	bool "Netlogic XLR SoC"

	depends on SYS_HAS_CPU_XLR

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM
@@ -1728,6 +1751,7 @@ config CPU_XLP 
	select WEAK_ORDERING

	select WEAK_REORDERING_BEYOND_LLSC

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_MIPSR2

	select CPU_SUPPORTS_HUGEPAGES

	select MIPS_ASID_BITS_VARIABLE
@@ -1833,12 +1857,14 @@ config CPU_LOONGSON2 
	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_HUGEPAGES

	select ARCH_HAS_PHYS_TO_DMA

	select CPU_HAS_LOAD_STORE_LR



config CPU_LOONGSON1

	bool

	select CPU_MIPS32

	select CPU_MIPSR1

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_CPUFREQ
@@ -2452,6 +2478,13 @@ config XKS01 
config CPU_HAS_RIXI

	bool



config CPU_HAS_LOAD_STORE_LR

	bool

	help

	  CPU has support for unaligned load and store instructions:

	  LWL, LWR, SWL, SWR (Load/store word left/right).

	  LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit systems).



#

# Vectored interrupt mode is an R2 feature

#
@@ -2899,6 +2932,9 @@ config USE_OF 
	select OF_EARLY_FLATTREE

	select IRQ_DOMAIN



config UHI_BOOT

	bool



config BUILTIN_DTB

	bool

arch/mips/Makefile

+4 −7
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#



archscripts: scripts_basic

	$(Q)$(MAKE) $(build)=arch/mips/tools elf-entry

	$(Q)$(MAKE) $(build)=arch/mips/boot/tools relocs



KBUILD_DEFCONFIG := 32r2el_defconfig
@@ -230,6 +231,8 @@ toolchain-xpa := $(call cc-option-yn,$(xpa-cflags-y) -mxpa) 
cflags-$(toolchain-xpa)			+= -DTOOLCHAIN_SUPPORTS_XPA

toolchain-crc				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc)

cflags-$(toolchain-crc)			+= -DTOOLCHAIN_SUPPORTS_CRC

toolchain-dsp				:= $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mdsp)

cflags-$(toolchain-dsp)			+= -DTOOLCHAIN_SUPPORTS_DSP



#

# Firmware support
@@ -257,13 +260,7 @@ ifdef CONFIG_PHYSICAL_START 
load-y					= $(CONFIG_PHYSICAL_START)

endif



# Sign-extend the entry point to 64 bits if retrieved as a 32-bit number.

entry-y		= $(shell $(OBJDUMP) -f vmlinux 2>/dev/null \

			| sed -n '/^start address / { \

				s/^.* //; \

				s/0x\([0-7].......\)$$/0x00000000\1/; \

				s/0x\(........\)$$/0xffffffff\1/; p }')



entry-y				= $(shell $(objtree)/arch/mips/tools/elf-entry vmlinux)

cflags-y			+= -I$(srctree)/arch/mips/include/asm/mach-generic

drivers-$(CONFIG_PCI)		+= arch/mips/pci/

arch/mips/bcm47xx/workarounds.c

+5 −3
Original line number Diff line number Diff line
@@ -5,9 +5,8 @@ 
#include <bcm47xx_board.h>

#include <bcm47xx.h>



static void __init bcm47xx_workarounds_netgear_wnr3500l(void)

static void __init bcm47xx_workarounds_enable_usb_power(int usb_power)

{

	const int usb_power = 12;

	int err;



	err = gpio_request_one(usb_power, GPIOF_OUT_INIT_HIGH, "usb_power");
@@ -23,7 +22,10 @@ void __init bcm47xx_workarounds(void) 


	switch (board) {

	case BCM47XX_BOARD_NETGEAR_WNR3500L:

		bcm47xx_workarounds_netgear_wnr3500l();

		bcm47xx_workarounds_enable_usb_power(12);

		break;

	case BCM47XX_BOARD_NETGEAR_WNDR3400_V3:

		bcm47xx_workarounds_enable_usb_power(21);

		break;

	default:

		/* No workaround(s) needed */

arch/mips/bmips/setup.c

+1 −8
Original line number Diff line number Diff line
@@ -153,8 +153,6 @@ void __init plat_time_init(void) 
	mips_hpt_frequency = freq;

}



extern const char __appended_dtb;



void __init plat_mem_setup(void)

{

	void *dtb;
@@ -164,15 +162,10 @@ void __init plat_mem_setup(void) 
	ioport_resource.start = 0;

	ioport_resource.end = ~0;



#ifdef CONFIG_MIPS_ELF_APPENDED_DTB

	if (!fdt_check_header(&__appended_dtb))

		dtb = (void *)&__appended_dtb;

	else

#endif

	/* intended to somewhat resemble ARM; see Documentation/arm/Booting */

	if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)

		dtb = phys_to_virt(fw_arg2);

	else if (fw_passed_dtb) /* UHI interface */

	else if (fw_passed_dtb) /* UHI interface or appended dtb */

		dtb = (void *)fw_passed_dtb;

	else if (__dtb_start != __dtb_end)

		dtb = (void *)__dtb_start;

arch/mips/boot/dts/lantiq/danube.dtsi

+21 −21
Original line number Diff line number Diff line
@@ -10,12 +10,12 @@ 
		};

	};



	biu@1F800000 {

	biu@1f800000 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "lantiq,biu", "simple-bus";

		reg = <0x1F800000 0x800000>;

		ranges = <0x0 0x1F800000 0x7FFFFF>;

		reg = <0x1f800000 0x800000>;

		ranges = <0x0 0x1f800000 0x7fffff>;



		icu0: icu@80200 {

			#interrupt-cells = <1>;
@@ -24,18 +24,18 @@ 
			reg = <0x80200 0x120>;

		};



		watchdog@803F0 {

		watchdog@803f0 {

			compatible = "lantiq,wdt";

			reg = <0x803F0 0x10>;

			reg = <0x803f0 0x10>;

		};

	};



	sram@1F000000 {

	sram@1f000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "lantiq,sram";

		reg = <0x1F000000 0x800000>;

		ranges = <0x0 0x1F000000 0x7FFFFF>;

		reg = <0x1f000000 0x800000>;

		ranges = <0x0 0x1f000000 0x7fffff>;



		eiu0: eiu@101000 {

			#interrupt-cells = <1>;
@@ -66,41 +66,41 @@ 
		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "lantiq,fpi", "simple-bus";

		ranges = <0x0 0x10000000 0xEEFFFFF>;

		reg = <0x10000000 0xEF00000>;

		ranges = <0x0 0x10000000 0xeefffff>;

		reg = <0x10000000 0xef00000>;



		gptu@E100A00 {

		gptu@e100a00 {

			compatible = "lantiq,gptu-xway";

			reg = <0xE100A00 0x100>;

			reg = <0xe100a00 0x100>;

		};



		serial@E100C00 {

		serial@e100c00 {

			compatible = "lantiq,asc";

			reg = <0xE100C00 0x400>;

			reg = <0xe100c00 0x400>;

			interrupt-parent = <&icu0>;

			interrupts = <112 113 114>;

		};



		dma0: dma@E104100 {

		dma0: dma@e104100 {

			compatible = "lantiq,dma-xway";

			reg = <0xE104100 0x800>;

			reg = <0xe104100 0x800>;

		};



		ebu0: ebu@E105300 {

		ebu0: ebu@e105300 {

			compatible = "lantiq,ebu-xway";

			reg = <0xE105300 0x100>;

			reg = <0xe105300 0x100>;

		};



		pci0: pci@E105400 {

		pci0: pci@e105400 {

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			compatible = "lantiq,pci-xway";

			bus-range = <0x0 0x0>;

			ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000	/* pci memory */

				  0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */

				  0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */

			reg = <0x7000000 0x8000		/* config space */

				0xE105400 0x400>;	/* pci bridge */

				0xe105400 0x400>;	/* pci bridge */

		};

	};

};