Loading soc/swr-mstr-ctrl.c +24 −8 Original line number Diff line number Diff line Loading @@ -121,7 +121,7 @@ static bool swrm_lock_sleep(struct swr_mstr_ctrl *swrm); static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm); static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr); static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val); static int swrm_runtime_resume(struct device *dev); static u8 swrm_get_clk_div(int mclk_freq, int bus_clk_freq) { Loading Loading @@ -901,6 +901,8 @@ static int swrm_read(struct swr_master *master, u8 dev_num, u16 reg_addr, mutex_unlock(&swrm->devlock); pm_runtime_get_sync(swrm->dev); if (swrm->req_clk_switch) swrm_runtime_resume(swrm->dev); ret = swrm_cmd_fifo_rd_cmd(swrm, &val, dev_num, 0, reg_addr, len); if (!ret) Loading Loading @@ -934,6 +936,8 @@ static int swrm_write(struct swr_master *master, u8 dev_num, u16 reg_addr, mutex_unlock(&swrm->devlock); pm_runtime_get_sync(swrm->dev); if (swrm->req_clk_switch) swrm_runtime_resume(swrm->dev); ret = swrm_cmd_fifo_wr_cmd(swrm, reg_val, dev_num, 0, reg_addr); pm_runtime_put_autosuspend(swrm->dev); Loading Loading @@ -1925,16 +1929,22 @@ static irqreturn_t swr_mstr_interrupt(int irq, void *dev) swrm->intr_mask); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: dev_dbg(swrm->dev, "%s: SWR read FIFO overflow\n", __func__); value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS); dev_err(swrm->dev, "%s: SWR read FIFO overflow fifo status\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: dev_dbg(swrm->dev, "%s: SWR read FIFO underflow\n", __func__); value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS); dev_err(swrm->dev, "%s: SWR read FIFO underflow fifo status\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: dev_dbg(swrm->dev, "%s: SWR write FIFO overflow\n", __func__); value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS); dev_err(swrm->dev, "%s: SWR write FIFO overflow fifo status\n", __func__, value); swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR: Loading Loading @@ -2928,6 +2938,8 @@ static int swrm_runtime_resume(struct device *dev) else pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer); if (swrm->req_clk_switch) swrm->req_clk_switch = false; mutex_unlock(&swrm->reslock); trace_printk("%s: pm_runtime: resume done, state:%d\n", Loading Loading @@ -3217,8 +3229,12 @@ int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data) } mutex_lock(&swrm->mlock); if (swrm->clk_src != *(int *)data) { if (swrm->state == SWR_MSTR_UP) if (swrm->state == SWR_MSTR_UP) { swrm->req_clk_switch = true; swrm_device_suspend(&pdev->dev); if (swrm->state == SWR_MSTR_UP) swrm->req_clk_switch = false; } swrm->clk_src = *(int *)data; } mutex_unlock(&swrm->mlock); Loading soc/swr-mstr-ctrl.h +1 −0 Original line number Diff line number Diff line Loading @@ -179,6 +179,7 @@ struct swr_mstr_ctrl { bool dev_up; bool ipc_wakeup_triggered; bool aud_core_err; bool req_clk_switch; struct pm_qos_request pm_qos_req; enum swrm_pm_state pm_state; wait_queue_head_t pm_wq; Loading Loading
soc/swr-mstr-ctrl.c +24 −8 Original line number Diff line number Diff line Loading @@ -121,7 +121,7 @@ static bool swrm_lock_sleep(struct swr_mstr_ctrl *swrm); static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm); static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr); static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val); static int swrm_runtime_resume(struct device *dev); static u8 swrm_get_clk_div(int mclk_freq, int bus_clk_freq) { Loading Loading @@ -901,6 +901,8 @@ static int swrm_read(struct swr_master *master, u8 dev_num, u16 reg_addr, mutex_unlock(&swrm->devlock); pm_runtime_get_sync(swrm->dev); if (swrm->req_clk_switch) swrm_runtime_resume(swrm->dev); ret = swrm_cmd_fifo_rd_cmd(swrm, &val, dev_num, 0, reg_addr, len); if (!ret) Loading Loading @@ -934,6 +936,8 @@ static int swrm_write(struct swr_master *master, u8 dev_num, u16 reg_addr, mutex_unlock(&swrm->devlock); pm_runtime_get_sync(swrm->dev); if (swrm->req_clk_switch) swrm_runtime_resume(swrm->dev); ret = swrm_cmd_fifo_wr_cmd(swrm, reg_val, dev_num, 0, reg_addr); pm_runtime_put_autosuspend(swrm->dev); Loading Loading @@ -1925,16 +1929,22 @@ static irqreturn_t swr_mstr_interrupt(int irq, void *dev) swrm->intr_mask); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: dev_dbg(swrm->dev, "%s: SWR read FIFO overflow\n", __func__); value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS); dev_err(swrm->dev, "%s: SWR read FIFO overflow fifo status\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: dev_dbg(swrm->dev, "%s: SWR read FIFO underflow\n", __func__); value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS); dev_err(swrm->dev, "%s: SWR read FIFO underflow fifo status\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: dev_dbg(swrm->dev, "%s: SWR write FIFO overflow\n", __func__); value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS); dev_err(swrm->dev, "%s: SWR write FIFO overflow fifo status\n", __func__, value); swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR: Loading Loading @@ -2928,6 +2938,8 @@ static int swrm_runtime_resume(struct device *dev) else pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer); if (swrm->req_clk_switch) swrm->req_clk_switch = false; mutex_unlock(&swrm->reslock); trace_printk("%s: pm_runtime: resume done, state:%d\n", Loading Loading @@ -3217,8 +3229,12 @@ int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data) } mutex_lock(&swrm->mlock); if (swrm->clk_src != *(int *)data) { if (swrm->state == SWR_MSTR_UP) if (swrm->state == SWR_MSTR_UP) { swrm->req_clk_switch = true; swrm_device_suspend(&pdev->dev); if (swrm->state == SWR_MSTR_UP) swrm->req_clk_switch = false; } swrm->clk_src = *(int *)data; } mutex_unlock(&swrm->mlock); Loading
soc/swr-mstr-ctrl.h +1 −0 Original line number Diff line number Diff line Loading @@ -179,6 +179,7 @@ struct swr_mstr_ctrl { bool dev_up; bool ipc_wakeup_triggered; bool aud_core_err; bool req_clk_switch; struct pm_qos_request pm_qos_req; enum swrm_pm_state pm_state; wait_queue_head_t pm_wq; Loading