ARM: dts: msm: Add Common driver, I2C and GSI DT nodes in trustedvm

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

	};

	soc: soc { };

};

&soc {

	#address-cells = <1>;

	#size-cells = <1>;

	ranges = <0 0 0 0xffffffff>;

	compatible = "simple-bus";

	/*

	 * QUPv3 Instances

	 * North 4 : SE 4

	 */

	/* QUPv3_0 wrapper instance: North QUP */

	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x9c0000 0x2000>;

	};

	/* GPI */

	gpi_dma0: qcom,gpi-dma@900000 {

		compatible = "qcom,gpi-dma";

		#dma-cells = <5>;

		reg = <0x900000 0x60000>;

		reg-names = "gpi-top";

		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;

		qcom,max-num-gpii = <12>;

		qcom,gpii-mask = <0x80>;

		qcom,ev-factor = <2>;

		qcom,gpi-ee-offset = <0x10000>;

		status = "ok";

	};

	/* I2C SE */

	qupv3_se4_i2c: i2c@990000 {

		compatible = "qcom,i2c-geni";

		reg = <0x990000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		dmas = <&gpi_dma0 0 4 3 64 0>,

			<&gpi_dma0 1 4 3 64 0>;

		dma-names = "tx", "rx";

		qcom,wrapper-core = <&qupv3_0>;

		qcom,le-vm;

		status = "ok";

	};

};

#include "trustedvm-ion.dtsi"