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Commit cadf97b1 authored by Chunming Zhou's avatar Chunming Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: clean up non-scheduler code path (v2) 



Non-scheduler code is longer supported.

v2: agd: rebased on upstream

Signed-off-by: default avatarChunming Zhou <David1.Zhou@amd.com>
Reviewed-by: default avatarKen Wang <Qingqing.Wang@amd.com>
Reviewed-by: default avatarMonk Liu <monk.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent be86c606

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −1
Original line number Diff line number Diff line
@@ -82,7 +82,6 @@ extern int amdgpu_vm_size; 
extern int amdgpu_vm_block_size;

extern int amdgpu_vm_fault_stop;

extern int amdgpu_vm_debug;

extern int amdgpu_enable_scheduler;

extern int amdgpu_sched_jobs;

extern int amdgpu_sched_hw_submission;

extern int amdgpu_enable_semaphores;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+1 −10
Original line number Diff line number Diff line
@@ -813,7 +813,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
	if (r)

		goto out;



	if (amdgpu_enable_scheduler && parser.num_ibs) {

	if (parser.num_ibs) {

		struct amdgpu_ring * ring = parser.ibs->ring;

		struct amd_sched_fence *fence;

		struct amdgpu_job *job;
@@ -858,15 +858,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 


		trace_amdgpu_cs_ioctl(job);

		amd_sched_entity_push_job(&job->base);



	} else {

		struct amdgpu_fence *fence;



		r = amdgpu_ib_schedule(adev, parser.num_ibs, parser.ibs,

				       parser.filp);

		fence = parser.ibs[parser.num_ibs - 1].fence;

		parser.fence = fence_get(&fence->base);

		cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;

	}



out:

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+22 −26
Original line number Diff line number Diff line
@@ -45,7 +45,6 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri, 
		ctx->rings[i].fences = (void *)ctx->fences + sizeof(struct fence *) *

			amdgpu_sched_jobs * i;

	}

	if (amdgpu_enable_scheduler) {

	/* create context entity for each ring */

	for (i = 0; i < adev->num_rings; i++) {

		struct amd_sched_rq *rq;
@@ -68,7 +67,6 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri, 
		kfree(ctx->fences);

		return r;

	}

	}

	return 0;

}
@@ -85,12 +83,10 @@ void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) 
			fence_put(ctx->rings[i].fences[j]);

	kfree(ctx->fences);



	if (amdgpu_enable_scheduler) {

	for (i = 0; i < adev->num_rings; i++)

		amd_sched_entity_fini(&adev->rings[i]->sched,

				      &ctx->rings[i].entity);

}

}



static int amdgpu_ctx_alloc(struct amdgpu_device *adev,

			    struct amdgpu_fpriv *fpriv,

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+0 −4
Original line number Diff line number Diff line
@@ -78,7 +78,6 @@ int amdgpu_vm_block_size = -1; 
int amdgpu_vm_fault_stop = 0;

int amdgpu_vm_debug = 0;

int amdgpu_exp_hw_support = 0;

int amdgpu_enable_scheduler = 1;

int amdgpu_sched_jobs = 32;

int amdgpu_sched_hw_submission = 2;

int amdgpu_powerplay = -1;
@@ -152,9 +151,6 @@ module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 
MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");

module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);



MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)");

module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444);



MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");

module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+19 −20
Original line number Diff line number Diff line
@@ -472,6 +472,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 
int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)

{

	int i, r;

	long timeout;



	ring->fence_drv.cpu_addr = NULL;

	ring->fence_drv.gpu_addr = 0;
@@ -486,8 +487,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) 


	init_waitqueue_head(&ring->fence_drv.fence_queue);



	if (amdgpu_enable_scheduler) {

		long timeout = msecs_to_jiffies(amdgpu_lockup_timeout);

	timeout = msecs_to_jiffies(amdgpu_lockup_timeout);

	if (timeout == 0) {

		/*

		 * FIXME:
@@ -506,7 +506,6 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) 
			  ring->name);

		return r;

	}

	}



	return 0;

}