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Commit ca84a522 authored by Ayush Kumar's avatar Ayush Kumar Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Correct csid clock rate in Blair Camera 

This change is to correct csid clock rate in Blair camera.

CRs-Fixed: 2944976
Change-Id: Ifb7dc37eac2df5530a9a7c7fec6dc6f69e067b97
parent e99ef36b

blair-camera.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -724,7 +724,7 @@ 
			<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_0_CLK>;

		clock-rates =

			<266570000 0 0 0 300000000 0>,

			<266571429 0 0 0 300000000 0>,

			<426400000 0 0 0 460800000 0>,

			<466500000 0 0 0 576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";
@@ -788,7 +788,7 @@ 
			<&gcc GCC_CAMSS_TFE_1_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_1_CLK>;

		clock-rates =

			<266570000 0 0 0 300000000 0>,

			<266571429 0 0 0 300000000 0>,

			<426400000 0 0 0 460800000 0>,

			<466500000 0 0 0 576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";
@@ -852,7 +852,7 @@ 
			<&gcc GCC_CAMSS_TFE_2_CLK_SRC>,

			<&gcc GCC_CAMSS_TFE_2_CLK>;

		clock-rates =

			<266570000 0 0 0 300000000 0>,

			<266571429 0 0 0 300000000 0>,

			<426400000 0 0 0 460800000 0>,

			<466500000 0 0 0 576000000 0>;

		clock-cntl-level = "svs", "svs_l1", "turbo";