Commit c9fd37f9 authored Sep 04, 2019 by Krishna Yarlagadda Committed by Greg Kroah-Hartman Sep 05, 2019

dt-binding: serial: tegra: add new chips

Add new compatible string for Tegra186. It differs from earlier chips
as it has FIFO mode enable check and 8 byte DMA buffer.
Add new compatible string for Tegra194. Tegra194 has different error
tolerance levels for baud rate compared to older chips.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Link: https://lore.kernel.org/r/1567572187-29820-6-git-send-email-kyarlagadda@nvidia.com

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent cb79f504

Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt

+6 −1

Original line number	Diff line number	Diff line
		NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.

		Required properties:
		- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
		- compatible : should be,
		"nvidia,tegra20-hsuart" for Tegra20,
		"nvidia,tegra30-hsuart" for Tegra30,
		"nvidia,tegra186-hsuart" for Tegra186,
		"nvidia,tegra194-hsuart" for Tegra194.

		- reg: Should contain UART controller registers location and length.
		- interrupts: Should contain UART controller interrupts.
		- clocks: Must contain one entry, for the module clock.