Merge tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

This binding uses the i.MX common pinctrl binding[3].

Required properties:

- compatible:		Should be "fsl,imx8qxp-iomuxc".

- compatible:		Should be one of:

			"fsl,imx8qm-iomuxc",

			"fsl,imx8qxp-iomuxc".

Required properties for Pinctrl sub nodes:

- fsl,pins:		Each entry consists of 3 integers which represents

			the mux and config setting for one pin. The first 2

			integers <pin_id mux_mode> are specified using a

			PIN_FUNC_ID macro, which can be found in

			<dt-bindings/pinctrl/pads-imx8qm.h>,

			<dt-bindings/pinctrl/pads-imx8qxp.h>.

			The last integer CONFIG is the pad setting value like

			pull-up on this pin.

Actions Semi S700 Pin Controller

This binding describes the pin controller found in the S700 SoC.

Required Properties:

- compatible:   Should be "actions,s700-pinctrl"

- reg:          Should contain the register base address and size of

		the pin controller.

- clocks:       phandle of the clock feeding the pin controller

- gpio-controller: Marks the device node as a GPIO controller.

- gpio-ranges: Specifies the mapping between gpio controller and

               pin-controller pins.

- #gpio-cells: Should be two. The first cell is the gpio pin number

		and the second cell is used for optional parameters.

- interrupt-controller: Marks the device node as an interrupt controller.

- #interrupt-cells: Specifies the number of cells needed to encode an

		interrupt.  Shall be set to 2.  The first cell

		defines the interrupt number, the second encodes

		the trigger flags described in

		bindings/interrupt-controller/interrupts.txt

- interrupts: The interrupt outputs from the controller. There is one GPIO

              interrupt per GPIO bank. The number of interrupts listed depends

              on the number of GPIO banks on the SoC. The interrupts must be

              ordered by bank, starting with bank 0.

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.

PIN CONFIGURATION NODES:

The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.

Pinmux functions are available only for the pin groups while pinconf

parameters are available for both pin groups and individual pins.

The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:

Required Properties:

- pins:		An array of strings, each string containing the name of a pin.

		These pins are used for selecting the pull control and schmitt

		trigger parameters. The following are the list of pins

		available:

		eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer,

		eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk,

		eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,

		i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,

		pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2,

		ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp,

		lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,

		lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,

		lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18,

		lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn,

		dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2,

		sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk,

		sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx,

		uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,

		uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk,

		i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1,

		csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3,

		sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2,

		dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb,

		dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0,

		dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2,

		dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3

- groups:       An array of strings, each string containing the name of a pin

                group. These pin groups are used for selecting the pinmux

                functions.

		rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp,

		rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp,

		rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp,

		i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,

		i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp,

		ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,

		dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp,

		lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp,

		dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp,

		uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp,

		sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,

		uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp,

		i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp,

		pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp,

		nand_ceb2_mfp, nand_ceb3_mfp

		These pin groups are used for selecting the drive strength

		parameters.

		sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv,

		rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv,

		smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv,

		pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv,

		dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv,

		uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv,

		sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv

- function:	An array of strings, each string containing the name of the

		pinmux functions. These functions can only be selected by

		the corresponding pin groups. The following are the list of

		pinmux functions available:

		nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1,

		uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,

		pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0,

		sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30,

		clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0

Optional Properties:

- bias-pull-down: No arguments. The specified pins should be configured as

		pull down.

- bias-pull-up:   No arguments. The specified pins should be configured as

		pull up.

- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified

		pins

- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified

		pins

- drive-strength: Integer. Selects the drive strength for the specified

		pins in mA.

		Valid values are:

		<2>

		<4>

		<8>

		<12>

Example:

	pinctrl: pinctrl@e01b0000 {

		compatible = "actions,s700-pinctrl";

		reg = <0x0 0xe01b0000 0x0 0x1000>;

		clocks = <&cmu CLK_GPIO>;

		gpio-controller;

		gpio-ranges = <&pinctrl 0 0 136>;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

                             <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

                             <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

                             <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

                             <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

		uart3-default: uart3-default {

			pinmux {

				groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp";

				function = "uart3";

			};

			pinconf {

				groups = "uart3_all_drv";

				drive-strength = <2>;

			};

		};

	};

  "allwinner,sun50i-h5-pinctrl"

  "allwinner,sun50i-h6-pinctrl"

  "allwinner,sun50i-h6-r-pinctrl"

  "allwinner,suniv-f1c100s-pinctrl"

  "nextthing,gr8-pinctrl"

- reg: Should contain the register physical address and length for the

required if you need to use the optional input-debounce property. Any new

device tree should set them.

Each pin bank, depending on the SoC, can have an associated regulator:

- vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs

- vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs

- vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs

- vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs

- vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs

- vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs

- vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs

- vcc-ph-supply: for the A31, A31s and A80 SoCs

- vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs

- vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs

Optional properties:

  - input-debounce: Array of debouncing periods in microseconds. One period per

    irq bank found in the controller. 0 if no setup required.

A list of pins varies across chipsets so few bindings are available.

Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"

noce.

Required properties:

- compatible: must be one of:

	"brcm,bcm4708-pinmux"

	"brcm,bcm4709-pinmux"

	"brcm,bcm53012-pinmux"

- reg: iomem address range of CRU (Central Resource Unit) pin registers

- reg-names: "cru_gpio_control" - the only needed & supported reg right now

- offset: offset of pin registers in the CRU block

Functions and their groups available for all chipsets:

- "spi": "spi_grp"

		#size-cells = <1>;

		cru@100 {

			compatible = "simple-bus";

			compatible = "syscon", "simple-mfd";

			reg = <0x100 0x1a4>;

			ranges;

			#address-cells = <1>;

			#size-cells = <1>;

			pin-controller@1c0 {

			pinctrl {

				compatible = "brcm,bcm4708-pinmux";

				reg = <0x1c0 0x24>;

				reg-names = "cru_gpio_control";

				offset = <0xc0>;

				spi-pins {

					function = "spi";

This binding doc is only for the IOMUXC1 support in A7 Domain and it only

supports generic pin config.

Please also refer pinctrl-bindings.txt in this directory for generic pinctrl

binding.

=== Pin Controller Node ===

Please refer to fsl,imx-pinctrl.txt in this directory for common binding

part and usage.

Required properties:

- compatible:	"fsl,imx7ulp-iomuxc1"

- reg:		Should contain the base physical address and size of the iomuxc

		registers.

=== Pin Configuration Node ===

- pinmux: One integers array, represents a group of pins mux setting.

	The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on

	a specific function.

	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux

	and config register as follows:

	<mux_conf_reg input_reg mux_mode input_val>

	Refer to imx7ulp-pinfunc.h in in device tree source folder for all

	available imx7ulp PIN_FUNC_ID.

Optional Properties:

- drive-strength		Integer. Controls Drive Strength

					0: Standard

					1: Hi Driver

- drive-push-pull		Bool. Enable Pin Push-pull

- drive-open-drain		Bool. Enable Pin Open-drian

- slew-rate:			Integer. Controls Slew Rate

					0: Standard

					1: Slow

- bias-disable:			Bool. Pull disabled

- bias-pull-down:		Bool. Pull down on pin

- bias-pull-up:			Bool. Pull up on pin

- compatible:	"fsl,imx7ulp-iomuxc1".

- fsl,pins:	Each entry consists of 5 integers which represents the mux

		and config setting for one pin. The first 4 integers

		<mux_conf_reg input_reg mux_mode input_val> are specified

		using a PIN_FUNC_ID macro, which can be found in

		imx7ulp-pinfunc.h in the device tree source folder.

		The last integer CONFIG is the pad setting value like

		pull-up on this pin.

		Please refer to i.MX7ULP Reference Manual for detailed

		CONFIG settings.

CONFIG bits definition:

PAD_CTL_OBE		(1 << 17)

PAD_CTL_IBE		(1 << 16)

PAD_CTL_LK		(1 << 16)

PAD_CTL_DSE_HI		(1 << 6)

PAD_CTL_DSE_STD		(0 << 6)

PAD_CTL_ODE		(1 << 5)

PAD_CTL_PUSH_PULL	(0 << 5)

PAD_CTL_SRE_SLOW	(1 << 2)

PAD_CTL_SRE_STD		(0 << 2)

PAD_CTL_PE		(1 << 0)

Examples:

#include "imx7ulp-pinfunc.h"

/* Pin Controller Node */

iomuxc1: iomuxc@40ac0000 {

iomuxc1: pinctrl@40ac0000 {

	compatible = "fsl,imx7ulp-iomuxc1";

	reg = <0x40ac0000 0x1000>;

	/* Pin Configuration Node */

	pinctrl_lpuart4: lpuart4grp {

		pinmux = <

			IMX7ULP_PAD_PTC3__LPUART4_RX

			IMX7ULP_PAD_PTC2__LPUART4_TX

		fsl,pins = <

			IMX7ULP_PAD_PTC3__LPUART4_RX	0x1

			IMX7ULP_PAD_PTC2__LPUART4_TX	0x1

		>;

		bias-pull-up;

	};

};