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Commit c9784a46 authored by Jie Yang's avatar Jie Yang Committed by Vinod Koul
Browse files

dmaengine: dw: fix a typo for bitfields of CTL_LO 



The offset of SINC should be 9, not 7, here fix this
typo.

Signed-off-by: default avatarJie Yang <yang.jie@intel.com>
Acked-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 92e963f5

drivers/dma/dw/regs.h

+1 −1
Original line number Diff line number Diff line
@@ -150,7 +150,7 @@ enum dw_dma_msize { 
#define DWC_CTLL_DST_INC	(0<<7)		/* DAR update/not */

#define DWC_CTLL_DST_DEC	(1<<7)

#define DWC_CTLL_DST_FIX	(2<<7)

#define DWC_CTLL_SRC_INC	(0<<7)		/* SAR update/not */

#define DWC_CTLL_SRC_INC	(0<<9)		/* SAR update/not */

#define DWC_CTLL_SRC_DEC	(1<<9)

#define DWC_CTLL_SRC_FIX	(2<<9)

#define DWC_CTLL_DST_MSIZE(n)	((n)<<11)	/* burst, #elements */