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Unverified Commit c95e3a4b authored by Annaliese McDermond's avatar Annaliese McDermond Committed by Mark Brown
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ASoC: tlv320aic32x4: Properly Set Processing Blocks 



Different processing blocks are required for different sampling
rates and power parameters.  Set the processing blocks based
on this information.

Signed-off-by: default avatarAnnaliese McDermond <nh6z@nh6z.net>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent b87d37d0

sound/soc/codecs/tlv320aic32x4.c

+36 −20
Original line number Diff line number Diff line
@@ -59,6 +59,8 @@ struct aic32x4_rate_divs { 
	u8 nadc;

	u8 madc;

	u8 blck_N;

	u8 r_block;

	u8 p_block;

};



struct aic32x4_priv {
@@ -307,34 +309,34 @@ static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 


static const struct aic32x4_rate_divs aic32x4_divs[] = {

	/* 8k rate */

	{12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},

	{24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},

	{25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},

	{12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24, 1, 1},

	{24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24, 1, 1},

	{25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24, 1, 1},

	/* 11.025k rate */

	{12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},

	{24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},

	{12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16, 1, 1},

	{24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16, 1, 1},

	/* 16k rate */

	{12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},

	{24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},

	{25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},

	{12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12, 1, 1},

	{24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12, 1, 1},

	{25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12, 1, 1},

	/* 22.05k rate */

	{12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},

	{24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},

	{25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},

	{12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8, 1, 1},

	{24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8, 1, 1},

	{25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8, 1, 1},

	/* 32k rate */

	{12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},

	{24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},

	{12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6, 1, 1},

	{24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6, 1, 1},

	/* 44.1k rate */

	{12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},

	{24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},

	{25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},

	{12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4, 1, 1},

	{24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4, 1, 1},

	{25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4, 1, 1},

	/* 48k rate */

	{12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},

	{24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},

	{25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4},

	{12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4, 1, 1},

	{24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4, 1, 1},

	{25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4, 1, 1},



	/* 96k rate */

	{25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1},

	{25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1, 1, 9},

};



static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
@@ -696,6 +698,18 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 
	return 0;

}



static int aic32x4_set_processing_blocks(struct snd_soc_component *component,

						u8 r_block, u8 p_block)

{

	if (r_block > 18 || p_block > 25)

		return -EINVAL;



	snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);

	snd_soc_component_write(component, AIC32X4_DACSPB, p_block);



	return 0;

}



static int aic32x4_setup_clocks(struct snd_soc_component *component,

				unsigned int sample_rate,

				unsigned int parent_rate)
@@ -708,6 +722,8 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, 
		return i;

	}



	aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);



	/* MCLK as PLL_CLKIN */

	snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,

			    AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);