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Commit c955bf39 authored by Chen Zhong's avatar Chen Zhong Committed by Stephen Boyd
Browse files

clk: mediatek: add the option for determining PLL source clock 



Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.

Signed-off-by: default avatarChen Zhong <chen.zhong@mediatek.com>
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 808ecf4a

drivers/clk/mediatek/clk-mtk.h

+1 −0
Original line number Diff line number Diff line
@@ -218,6 +218,7 @@ struct mtk_pll_data { 
	uint32_t pcw_reg;

	int pcw_shift;

	const struct mtk_pll_div_table *div_table;

	const char *parent_name;

};



void mtk_clk_register_plls(struct device_node *node,

drivers/clk/mediatek/clk-pll.c

+4 −1
Original line number Diff line number Diff line
@@ -312,6 +312,9 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, 
	init.name = data->name;

	init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;

	init.ops = &mtk_pll_ops;

	if (data->parent_name)

		init.parent_names = &data->parent_name;

	else

		init.parent_names = &parent_name;

	init.num_parents = 1;