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Commit c9460dcb authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
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arm64: capabilities: Merge entries for ARM64_WORKAROUND_CLEAN_CACHE 



We have two entries for ARM64_WORKAROUND_CLEAN_CACHE capability :

1) ARM Errata 826319, 827319, 824069, 819472 on A53 r0p[012]
2) ARM Errata 819472 on A53 r0p[01]

Both have the same work around. Merge these entries to avoid
duplicate entries for a single capability. Add a new Kconfig
entry to control the "capability" entry to make it easier
to handle combinations of the CONFIGs.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 3bbd3db8

arch/arm64/Kconfig

+7 −0
Original line number Original line Diff line number Diff line
@@ -313,9 +313,13 @@ menu "Kernel Features" 




menu "ARM errata workarounds via the alternatives framework"

menu "ARM errata workarounds via the alternatives framework"





config ARM64_WORKAROUND_CLEAN_CACHE

	def_bool n



config ARM64_ERRATUM_826319

config ARM64_ERRATUM_826319

	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"

	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"

	default y

	default y

	select ARM64_WORKAROUND_CLEAN_CACHE

	help

	help

	  This option adds an alternative code sequence to work around ARM

	  This option adds an alternative code sequence to work around ARM

	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or

	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
@@ -337,6 +341,7 @@ config ARM64_ERRATUM_826319 
config ARM64_ERRATUM_827319

config ARM64_ERRATUM_827319

	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"

	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"

	default y

	default y

	select ARM64_WORKAROUND_CLEAN_CACHE

	help

	help

	  This option adds an alternative code sequence to work around ARM

	  This option adds an alternative code sequence to work around ARM

	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI

	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
@@ -358,6 +363,7 @@ config ARM64_ERRATUM_827319 
config ARM64_ERRATUM_824069

config ARM64_ERRATUM_824069

	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"

	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"

	default y

	default y

	select ARM64_WORKAROUND_CLEAN_CACHE

	help

	help

	  This option adds an alternative code sequence to work around ARM

	  This option adds an alternative code sequence to work around ARM

	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected

	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
@@ -380,6 +386,7 @@ config ARM64_ERRATUM_824069 
config ARM64_ERRATUM_819472

config ARM64_ERRATUM_819472

	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"

	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"

	default y

	default y

	select ARM64_WORKAROUND_CLEAN_CACHE

	help

	help

	  This option adds an alternative code sequence to work around ARM

	  This option adds an alternative code sequence to work around ARM

	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache

	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache

arch/arm64/include/asm/cputype.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -151,6 +151,7 @@ struct midr_range { 
		.rv_max = MIDR_CPU_VAR_REV(v_max, r_max),	\

		.rv_max = MIDR_CPU_VAR_REV(v_max, r_max),	\

	}

	}





#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)

#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)

#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)





static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)

static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)

arch/arm64/kernel/cpu_errata.c

+16 −12
Original line number Original line Diff line number Diff line
@@ -570,24 +570,28 @@ static const struct midr_range arm64_harden_el2_vectors[] = { 




#endif

#endif





const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

static const struct midr_range workaround_clean_cache[] = {

#if	defined(CONFIG_ARM64_ERRATUM_826319) || \

#if	defined(CONFIG_ARM64_ERRATUM_826319) || \

	defined(CONFIG_ARM64_ERRATUM_827319) || \

	defined(CONFIG_ARM64_ERRATUM_827319) || \

	defined(CONFIG_ARM64_ERRATUM_824069)

	defined(CONFIG_ARM64_ERRATUM_824069)

	{

	/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */

	/* Cortex-A53 r0p[012] */

	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),

		.desc = "ARM errata 826319, 827319, 824069",

		.capability = ARM64_WORKAROUND_CLEAN_CACHE,

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),

		.cpu_enable = cpu_enable_cache_maint_trap,

	},

#endif

#endif

#ifdef	CONFIG_ARM64_ERRATUM_819472

#ifdef	CONFIG_ARM64_ERRATUM_819472

	/* Cortex-A53 r0p[01] : ARM errata 819472 */

	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),

#endif

	{},

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{

	{

	/* Cortex-A53 r0p[01] */

		.desc = "ARM errata 826319, 827319, 824069, 819472",

		.desc = "ARM errata 819472",

		.capability = ARM64_WORKAROUND_CLEAN_CACHE,

		.capability = ARM64_WORKAROUND_CLEAN_CACHE,

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),

		ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),

		.cpu_enable = cpu_enable_cache_maint_trap,

		.cpu_enable = cpu_enable_cache_maint_trap,

	},

	},

#endif

#endif