dt-bindings: mmc: sprd: Add PHY DLL delay documentation

- assigned-clocks: the same with "sdio" clock

- assigned-clock-parents: the default parent of "sdio" clock

PHY DLL delays are used to delay the data valid window, and align the window

to sampling clock. PHY DLL delays can be configured by following properties,

and each property contains 4 cells which are used to configure the clock data

write line delay value, clock read command line delay value, clock read data

positive edge delay value and clock read data negative edge delay value.

Each cell's delay value unit is cycle of the PHY clock.

- sprd,phy-delay-legacy: Delay value for legacy timing.

- sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.

- sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.

- sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.

- sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.

- sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.

- sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.

- sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.

- sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.

Examples:

sdio0: sdio@20600000 {

	assigned-clocks = <&ap_clk CLK_EMMC_2X>;

	assigned-clock-parents = <&rpll CLK_RPLL_390M>;

	sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;

	bus-width = <8>;

	non-removable;

	no-sdio;