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Commit c8ece5af authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Add support for A643 GPU"

parents fe457050 da59d144

drivers/gpu/msm/adreno-gpulist.h

+33 −0
Original line number Original line Diff line number Diff line
@@ -1746,6 +1746,38 @@ static const struct adreno_a6xx_core adreno_gpu_core_a642l = { 
	.ctxt_record_size = 2496 * 1024,

	.ctxt_record_size = 2496 * 1024,

};

};





static const struct adreno_a6xx_core adreno_gpu_core_a643 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A643, ANY_ID, ANY_ID, ANY_ID, ANY_ID),

		.compatible = "qcom,adreno-gpu-a643",

		.features = ADRENO_RPMH | ADRENO_GPMU | ADRENO_APRIV |

				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

				ADRENO_PREEMPTION | ADRENO_IFPC | ADRENO_BCL,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_size = SZ_512K,

		.bus_width = 32,

		.snapshot_size = SZ_2M,

	},

	.prim_fifo_threshold = 0x00200000,

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a660_sqe.fw",

	.gmufw_name = "a660_gmu.bin",

	.zap_name = "a660_zap",

	.hwcg = a660_hwcg_regs,

	.hwcg_count = ARRAY_SIZE(a660_hwcg_regs),

	.vbif = a650_gbif_regs,

	.vbif_count = ARRAY_SIZE(a650_gbif_regs),

	.hang_detect_cycles = 0x3ffff,

	.veto_fal10 = true,

	.protected_regs = a660_protected_regs,

	.disable_tseskip = true,

	.highest_bank_bit = 15,

	.pdc_in_aop = true,

	.ctxt_record_size = 2496 * 1024,

};



static const struct adreno_reglist a702_hwcg_regs[] = {

static const struct adreno_reglist a702_hwcg_regs[] = {

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
@@ -1863,5 +1895,6 @@ static const struct adreno_gpu_core *adreno_gpulist[] = { 
	&adreno_gpu_core_a610.base,

	&adreno_gpu_core_a610.base,

	&adreno_gpu_core_a642.base,

	&adreno_gpu_core_a642.base,

	&adreno_gpu_core_a642l.base,

	&adreno_gpu_core_a642l.base,

	&adreno_gpu_core_a643.base,

	&adreno_gpu_core_a702.base,

	&adreno_gpu_core_a702.base,

};
 
};

drivers/gpu/msm/adreno.h

+5 −3
Original line number Original line Diff line number Diff line
@@ -202,6 +202,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A630 = 630,

	ADRENO_REV_A630 = 630,

	ADRENO_REV_A640 = 640,

	ADRENO_REV_A640 = 640,

	ADRENO_REV_A642 = 642,

	ADRENO_REV_A642 = 642,

	ADRENO_REV_A643 = 643,

	ADRENO_REV_A650 = 650,

	ADRENO_REV_A650 = 650,

	ADRENO_REV_A660 = 660,

	ADRENO_REV_A660 = 660,

	ADRENO_REV_A680 = 680,

	ADRENO_REV_A680 = 680,
@@ -1074,17 +1075,18 @@ ADRENO_TARGET(a619, ADRENO_REV_A619) 
ADRENO_TARGET(a620, ADRENO_REV_A620)

ADRENO_TARGET(a620, ADRENO_REV_A620)

ADRENO_TARGET(a630, ADRENO_REV_A630)

ADRENO_TARGET(a630, ADRENO_REV_A630)

ADRENO_TARGET(a640, ADRENO_REV_A640)

ADRENO_TARGET(a640, ADRENO_REV_A640)

ADRENO_TARGET(a643, ADRENO_REV_A643)

ADRENO_TARGET(a650, ADRENO_REV_A650)

ADRENO_TARGET(a650, ADRENO_REV_A650)

ADRENO_TARGET(a680, ADRENO_REV_A680)

ADRENO_TARGET(a680, ADRENO_REV_A680)

ADRENO_TARGET(a702, ADRENO_REV_A702)

ADRENO_TARGET(a702, ADRENO_REV_A702)





/* A642 and A642L are derived from A660 and shares same logic */

/* A642, A642L and A643 are derived from A660 and shares same logic */

static inline int adreno_is_a660(struct adreno_device *adreno_dev)

static inline int adreno_is_a660(struct adreno_device *adreno_dev)

{

{

	unsigned int rev = ADRENO_GPUREV(adreno_dev);

	unsigned int rev = ADRENO_GPUREV(adreno_dev);





	return (rev == ADRENO_REV_A660 || adreno_is_a642(adreno_dev) ||

	return (rev == ADRENO_REV_A660 || adreno_is_a642(adreno_dev) ||

		adreno_is_a642l(adreno_dev));

		adreno_is_a642l(adreno_dev) || adreno_is_a643(adreno_dev));

}

}





/*

/*
@@ -1123,7 +1125,7 @@ static inline int adreno_is_a650_family(struct adreno_device *adreno_dev) 




	return (rev == ADRENO_REV_A650 || rev == ADRENO_REV_A620 ||

	return (rev == ADRENO_REV_A650 || rev == ADRENO_REV_A620 ||

		rev == ADRENO_REV_A660 || adreno_is_a642(adreno_dev) ||

		rev == ADRENO_REV_A660 || adreno_is_a642(adreno_dev) ||

		adreno_is_a642l(adreno_dev));

		adreno_is_a642l(adreno_dev) || rev == ADRENO_REV_A643);

}

}





static inline int adreno_is_a619_holi(struct adreno_device *adreno_dev)

static inline int adreno_is_a619_holi(struct adreno_device *adreno_dev)

drivers/gpu/msm/adreno_a6xx.c

+8 −3
Original line number Original line Diff line number Diff line
@@ -175,7 +175,8 @@ int a6xx_init(struct adreno_device *adreno_dev) 
	/* If the memory type is DDR 4, override the existing configuration */

	/* If the memory type is DDR 4, override the existing configuration */

	if (of_fdt_get_ddrtype() == 0x7) {

	if (of_fdt_get_ddrtype() == 0x7) {

		if (adreno_is_a642(adreno_dev) ||

		if (adreno_is_a642(adreno_dev) ||

			adreno_is_a642l(adreno_dev))

			adreno_is_a642l(adreno_dev) ||

			adreno_is_a643(adreno_dev))

			adreno_dev->highest_bank_bit = 14;

			adreno_dev->highest_bank_bit = 14;

		else if ((adreno_is_a650(adreno_dev) ||

		else if ((adreno_is_a650(adreno_dev) ||

				adreno_is_a660(adreno_dev)))

				adreno_is_a660(adreno_dev)))
@@ -822,8 +823,12 @@ void a6xx_start(struct adreno_device *adreno_dev) 
		kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, 0x1);

		kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, 0x1);

		kgsl_regwrite(device, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);

		kgsl_regwrite(device, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);





		/* Set dualQ + disable afull for A660, A642 GPU but not for A642L */

		/*

		if (!adreno_is_a642l(adreno_dev))

		 * Set dualQ + disable afull for A660, A642 GPU but

		 * not for A642L and A643

		 */

		if (!adreno_is_a642l(adreno_dev) ||

			!adreno_is_a643(adreno_dev))

			kgsl_regwrite(device, A6XX_UCHE_CMDQ_CONFIG, 0x66906);

			kgsl_regwrite(device, A6XX_UCHE_CMDQ_CONFIG, 0x66906);

	}

	}