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Commit c8c3798d authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Catalin Marinas
Browse files

arm64: v8.3: Support for Javascript conversion instruction 



ARMv8.3 adds support for a new instruction to perform conversion
from double precision floating point to integer  to match the
architected behaviour of the equivalent Javascript conversion.
Expose the availability via HWCAP and MRS emulation.

Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 87da236e

Documentation/arm64/cpu-feature-registers.txt

+8 −0
Original line number Diff line number Diff line
@@ -169,6 +169,14 @@ infrastructure: 
   as available on the CPU where it is fetched and is not a system

   wide safe value.



  4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1



     x--------------------------------------------------x

     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | JSCVT                        | [15-12] |    y    |

     x--------------------------------------------------x



Appendix I: Example

---------------------------

arch/arm64/include/asm/sysreg.h

+3 −0
Original line number Diff line number Diff line
@@ -156,6 +156,9 @@ 
#define ID_AA64ISAR0_SHA1_SHIFT		8

#define ID_AA64ISAR0_AES_SHIFT		4



/* id_aa64isar1 */

#define ID_AA64ISAR1_JSCVT_SHIFT	12



/* id_aa64pfr0 */

#define ID_AA64PFR0_GIC_SHIFT		24

#define ID_AA64PFR0_ASIMD_SHIFT		20

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -32,5 +32,6 @@ 
#define HWCAP_ASIMDHP		(1 << 10)

#define HWCAP_CPUID		(1 << 11)

#define HWCAP_ASIMDRDM		(1 << 12)

#define HWCAP_JSCVT		(1 << 13)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+7 −1
Original line number Diff line number Diff line
@@ -97,6 +97,11 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),

	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
@@ -314,7 +319,7 @@ static const struct __ftr_reg_entry { 


	/* Op1 = 0, CRn = 0, CRm = 6 */

	ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),

	ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_raz),

	ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),



	/* Op1 = 0, CRn = 0, CRm = 7 */

	ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
@@ -888,6 +893,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),

	{},

};

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ static const char *const hwcap_str[] = { 
	"asimdhp",

	"cpuid",

	"asimdrdm",

	"jscvt",

	NULL

};