iommu/vt-d: Allow to flush more than 4GB of device TLBs



The shift qi_flush_dev_iotlb() is done on an int, which
limits the mask to 32 bits. Make the mask 64 bits wide so
that more than 4GB of address range can be flushed at once.

Signed-off-by: Joerg Roedel <jroedel@suse.de>

parent 9003d618

drivers/iommu/dmar.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1343,7 +1343,7 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,

		if (mask) {
		BUG_ON(addr & ((1 << (VTD_PAGE_SHIFT + mask)) - 1));
		addr \|= (1 << (VTD_PAGE_SHIFT + mask - 1)) - 1;
		addr \|= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
		desc.high = QI_DEV_IOTLB_ADDR(addr) \| QI_DEV_IOTLB_SIZE;
		} else
		desc.high = QI_DEV_IOTLB_ADDR(addr);