Commit c887f5b0 authored Mar 05, 2018 by Daniel Schultz Committed by Heiko Stuebner Apr 16, 2018

ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som



The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

parent 5f501b42

arch/arm/boot/dts/rk3288-phycore-som.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -151,6 +151,7 @@
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		enet-phy-lane-no-swap;
		ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
		};
		};
		};