ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som

The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>