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Commit c88580e1 authored by Shahar S Matityahu's avatar Shahar S Matityahu Committed by Luca Coelho
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iwlwifi: dbg: add DRAM monitor support for AX210 device family



Allows to perform monitor dumping on AX210 device family

Signed-off-by: default avatarShahar S Matityahu <shahar.s.matityahu@intel.com>
Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent a15d4f3b
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+5 −1
Original line number Diff line number Diff line
@@ -211,6 +211,9 @@ struct iwl_fw_error_dump_info {
 * @fw_mon_wr_ptr: the position of the write pointer in the cyclic buffer
 * @fw_mon_base_ptr: base pointer of the data
 * @fw_mon_cycle_cnt: number of wraparounds
 * @fw_mon_base_high_ptr: used in AX210 devices, the base adderss is 64 bit
 *	so fw_mon_base_ptr holds LSB 32 bits and fw_mon_base_high_ptr hold
 *	MSB 32 bits
 * @reserved: for future use
 * @data: captured data
 */
@@ -218,7 +221,8 @@ struct iwl_fw_error_dump_fw_mon {
	__le32 fw_mon_wr_ptr;
	__le32 fw_mon_base_ptr;
	__le32 fw_mon_cycle_cnt;
	__le32 reserved[3];
	__le32 fw_mon_base_high_ptr;
	__le32 reserved[2];
	u8 data[];
} __packed;

+6 −0
Original line number Diff line number Diff line
@@ -368,6 +368,12 @@
#define MON_BUFF_WRPTR_VER2		(0xa03c24)
#define MON_BUFF_CYCLE_CNT_VER2		(0xa03c28)
#define MON_BUFF_SHIFT_VER2		(0x8)
/* FW monitor familiy AX210 and on */
#define DBGC_CUR_DBGBUF_BASE_ADDR_LSB		(0xd03c20)
#define DBGC_CUR_DBGBUF_BASE_ADDR_MSB		(0xd03c24)
#define DBGC_CUR_DBGBUF_STATUS			(0xd03c1c)
#define DBGC_DBGBUF_WRAP_AROUND			(0xd03c2c)
#define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK	(0x00ffffff)

#define MON_DMARB_RD_CTL_ADDR		(0xa03c60)
#define MON_DMARB_RD_DATA_ADDR		(0xa03c5c)
+20 −9
Original line number Diff line number Diff line
@@ -3012,10 +3012,14 @@ static void
iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
			     struct iwl_fw_error_dump_fw_mon *fw_mon_data)
{
	u32 base, write_ptr, wrap_cnt;

	/* If there was a dest TLV - use the values from there */
	if (trans->ini_valid) {
	u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;

	if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
		base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
		base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
		write_ptr = DBGC_CUR_DBGBUF_STATUS;
		wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
	} else if (trans->ini_valid) {
		base = iwl_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2);
		write_ptr = iwl_umac_prph(trans, MON_BUFF_WRPTR_VER2);
		wrap_cnt = iwl_umac_prph(trans, MON_BUFF_CYCLE_CNT_VER2);
@@ -3028,12 +3032,18 @@ iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
		write_ptr = MON_BUFF_WRPTR;
		wrap_cnt = MON_BUFF_CYCLE_CNT;
	}
	fw_mon_data->fw_mon_wr_ptr =
		cpu_to_le32(iwl_read_prph(trans, write_ptr));

	write_ptr_val = iwl_read_prph(trans, write_ptr);
	fw_mon_data->fw_mon_cycle_cnt =
		cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
	fw_mon_data->fw_mon_base_ptr =
		cpu_to_le32(iwl_read_prph(trans, base));
	if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
		fw_mon_data->fw_mon_base_high_ptr =
			cpu_to_le32(iwl_read_prph(trans, base_high));
		write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
	}
	fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
}

static u32
@@ -3044,9 +3054,10 @@ iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
	u32 len = 0;

	if ((trans->num_blocks &&
	     trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
	     (trans->dbg_dest_tlv && !trans->ini_valid) ||
	     (trans->ini_valid && trans->num_blocks)) {
	     (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
	      trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210 ||
	      trans->ini_valid)) ||
	    (trans->dbg_dest_tlv && !trans->ini_valid)) {
		struct iwl_fw_error_dump_fw_mon *fw_mon_data;

		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);