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Commit c832a7c9 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt
Browse files

msm: kgsl: Move rscc to a6xx gmu space 



Rscc registers are only needed for gmu based targets. So move the
probe and snapshot to a6xx gmu probe and snapshot respectively.
Also, fix the rscc offset for targets which have rscc registers
part of the gmu register space.

Change-Id: I3f73e3c99838d01676f81df6bc7bd7ab3334a0fe
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent 29607073

drivers/gpu/msm/a6xx_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -1122,7 +1122,7 @@ 
 * now we are using a separate section for RSCC regsiters. Add the

 * offset for backward compatibility.

 */

#define RSCC_OFFSET_LEGACY			0x23400

#define RSCC_OFFSET_LEGACY			0x23000



/* RGMU(PCC) registers in A6X_GMU_CX_0_NON_CONTEXT_DEC domain */

#define A6XX_RGMU_CX_INTR_GEN_EN		0x1F80F

drivers/gpu/msm/adreno.c

+0 −39
Original line number Diff line number Diff line
@@ -1110,25 +1110,6 @@ static void adreno_cx_misc_probe(struct kgsl_device *device) 
					res->start, adreno_dev->cx_misc_len);

}



static void adreno_rscc_probe(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct resource *res;



	res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,

						"rscc");



	if (res == NULL)

		return;



	adreno_dev->rscc_base = res->start - device->reg_phys;

	adreno_dev->rscc_len = resource_size(res);

	adreno_dev->rscc_virt = devm_ioremap(&device->pdev->dev, res->start,

						adreno_dev->rscc_len);

	if (adreno_dev->rscc_virt == NULL)

		dev_warn(device->dev, "rscc ioremap failed\n");

}



static void adreno_isense_probe(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
@@ -1379,8 +1360,6 @@ int adreno_device_probe(struct platform_device *pdev, 
	/* Probe for the optional CX_MISC block */

	adreno_cx_misc_probe(device);



	adreno_rscc_probe(device);



	adreno_isense_probe(device);



	/* Allocate the memstore for storing timestamps and other useful info */
@@ -3144,24 +3123,6 @@ void adreno_cx_misc_regread(struct adreno_device *adreno_dev, 
	 */

	rmb();

}

void adreno_rscc_regread(struct adreno_device *adreno_dev,

	unsigned int offsetwords, unsigned int *value)

{

	unsigned int rscc_offset;



	rscc_offset = (offsetwords << 2);

	if (!adreno_dev->rscc_virt ||

		(rscc_offset >= adreno_dev->rscc_len))

		return;



	*value =  __raw_readl(adreno_dev->rscc_virt + rscc_offset);



	/*

	 * ensure this read finishes before the next one.

	 * i.e. act like normal readl()

	 */

	rmb();

}



void adreno_isense_regread(struct adreno_device *adreno_dev,

	unsigned int offsetwords, unsigned int *value)

drivers/gpu/msm/adreno.h

+0 −8
Original line number Diff line number Diff line
@@ -405,9 +405,6 @@ struct adreno_gpu_core { 
 * @chipid: Chip ID specific to the GPU

 * @cx_misc_len: Length of the CX MISC register block

 * @cx_misc_virt: Pointer where the CX MISC block is mapped

 * @rscc_base: Base physical address of the RSCC

 * @rscc_len: Length of the RSCC register block

 * @rscc_virt: Pointer where RSCC block is mapped

 * @isense_base: Base physical address of isense block

 * @isense_len: Length of the isense register block

 * @isense_virt: Pointer where isense block is mapped
@@ -487,9 +484,6 @@ struct adreno_device { 
	void __iomem *cx_dbgc_virt;

	unsigned int cx_misc_len;

	void __iomem *cx_misc_virt;

	unsigned long rscc_base;

	unsigned int rscc_len;

	void __iomem *rscc_virt;

	unsigned long isense_base;

	unsigned int isense_len;

	void __iomem *isense_virt;
@@ -978,8 +972,6 @@ void adreno_cx_misc_regwrite(struct adreno_device *adreno_dev, 
void adreno_cx_misc_regrmw(struct adreno_device *adreno_dev,

		unsigned int offsetwords,

		unsigned int mask, unsigned int bits);

void adreno_rscc_regread(struct adreno_device *adreno_dev,

		unsigned int offsetwords, unsigned int *value);

void adreno_isense_regread(struct adreno_device *adreno_dev,

		unsigned int offsetwords, unsigned int *value);

drivers/gpu/msm/adreno_a6xx.h

+0 −33
Original line number Diff line number Diff line
@@ -224,39 +224,6 @@ static inline int timed_poll_check(struct kgsl_device *device, 
	return 0;

}



static inline int timed_poll_check_rscc(struct kgsl_device *device,

		unsigned int offset, unsigned int expected_ret,

		unsigned int timeout, unsigned int mask)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	unsigned long t;

	unsigned int value;



	if (!adreno_is_a650_family(adreno_dev))

		return timed_poll_check(device, offset + RSCC_OFFSET_LEGACY,

				expected_ret, timeout, mask);



	t = jiffies + msecs_to_jiffies(timeout);



	do {

		adreno_rscc_regread(adreno_dev, offset, &value);



		if ((value & mask) == expected_ret)

			return 0;

		/* Wait 100us to reduce unnecessary AHB bus traffic */

		usleep_range(10, 100);

	} while (!time_after(jiffies, t));



	/* Double check one last time */

	if (adreno_is_a650_family(adreno_dev))

		adreno_rscc_regread(adreno_dev, offset, &value);



	if ((value & mask) == expected_ret)

		return 0;



	return -ETIMEDOUT;

}



/* Preemption functions */

void a6xx_preemption_trigger(struct adreno_device *adreno_dev);

void a6xx_preemption_schedule(struct adreno_device *adreno_dev);

drivers/gpu/msm/adreno_a6xx_gmu.c

+30 −6
Original line number Diff line number Diff line
@@ -102,6 +102,22 @@ static struct gmu_iommu_context a6xx_gmu_ctx[] = { 
	[GMU_CONTEXT_KERNEL] = { .name = "gmu_kernel" }

};



static int timed_poll_check_rscc(struct kgsl_device *device,

		unsigned int offset, unsigned int expected_ret,

		unsigned int timeout, unsigned int mask)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);

	u32 value;



	if (!adreno_is_a650_family(adreno_dev))

		return timed_poll_check(device, offset + RSCC_OFFSET_LEGACY,

				expected_ret, timeout, mask);



	return readl_poll_timeout(gmu->rscc_virt + (offset << 2), value,

		(value & mask) == expected_ret, 100, timeout * 1000);

}



void gmu_fault_snapshot(struct kgsl_device *device)

{

	device->gmu_fault = true;
@@ -139,10 +155,11 @@ static void _regwrite(void __iomem *regbase, 
static void a6xx_load_rsc_ucode(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);

	void __iomem *rscc;



	if (adreno_is_a650_family(adreno_dev))

		rscc = adreno_dev->rscc_virt;

		rscc = gmu->rscc_virt;

	else

		rscc = device->gmu_core.reg_virt + 0x23000;
@@ -2062,11 +2079,6 @@ static int a6xx_gmu_first_boot(struct adreno_device *adreno_dev) 
	struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);

	int level, ret;



	if (adreno_is_a650_family(adreno_dev) && !adreno_dev->rscc_virt) {

		dev_err(&gmu->pdev->dev, "RSCC registers not mapped\n");

		return -EINVAL;

	}



	ret = a6xx_gmu_aop_send_acd_state(gmu->mailbox.channel,

			adreno_dev->acd_enabled);

	if (ret) {
@@ -2552,6 +2564,7 @@ static int a6xx_gmu_probe(struct kgsl_device *device, 
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev);

	struct a6xx_hfi *hfi = &gmu->hfi;

	struct resource *res;

	int ret;



	gmu->pdev = pdev;
@@ -2560,6 +2573,17 @@ static int a6xx_gmu_probe(struct kgsl_device *device, 
	gmu->pdev->dev.dma_mask = &gmu->pdev->dev.coherent_dma_mask;

	set_dma_ops(&gmu->pdev->dev, NULL);



	res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,

						"rscc");

	if (res) {

		gmu->rscc_virt = devm_ioremap(&device->pdev->dev, res->start,

						resource_size(res));

		if (gmu->rscc_virt == NULL) {

			dev_err(&gmu->pdev->dev, "rscc ioremap failed\n");

			return -ENOMEM;

		}

	}



	/* Set up GMU regulators */

	ret = a6xx_gmu_regulators_probe(gmu, pdev);

	if (ret)